Datasheet

12
LT1204
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
When the decoder turns off the tee switch (Q2 on) the
emitter base junctions of Q1 and Q3 become reverse-
biased while Q2 emitter absorbs current from I
1
. Not only
do the reverse-biased emitter base junctions provide good
isolation, but any signal at V
IN0
coupling to Q1 emitter is
further attenuated by the shunt impedance of Q2 emitter.
Current from I
2
is routed to any on switch.
Crosstalk performance is a strong function of the IC
package, the PC board layout as well as the IC design. The
die layout utilizes grounds between each input to isolate
adjacent channels, while the output and feedback pins are
on opposite sides of the die from the input. The layout of
a PC board that is capable of providing –90dB all hostile
crosstalk at 10MHz is not trivial. That level corresponds to
a 30µV output below a 1V input at 10MHz. A demonstra-
tion board has been fabricated to show the component and
ground placement required to attain these crosstalk num-
bers. A graph of all hostile crosstalk for both the PDIP and
SO packages is shown. It has been found empirically from
these PC boards that capacitive coupling across the pack-
age of greater than 3fF (0.003pF) will diminish the rejec-
tion, and it is recommended that this proven layout be
copied into designs. The key to the success of the SO PC
board #028 is the use of a ground plane guard around Pin
13, the feedback pin.
PDIP PC Board #029, Component Side
1204 AI09
GND V– V+
[phone]
LT1204 VIDEO MUX
DEMONSTRATION BOARD
VIN0
VIN1
VIN2
VIN3
R1
R2
R6
C4
C2
C1
C3
U1
R3
RF
RO
VOUT
ENABLE
R1
R0
S/D
REF
+
+
FREQUENCY (MHz)
1
–120
ALL HOSTILE CROSSTALK (dB)
–100
–80
–60
–40
10 100
1204 AI07
–20
V
S
= ±15V
V
IN0
= GND
V
IN1,2,3
= 0dBm
R
L
= 100Ω
PDIP
DEMO PCB #029
SO
DEMO PCB #028
All Hostile Crosstalk