Datasheet

5
LT1169
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
Input Bias and Offset Currents
Over the Common Mode Range
Input Bias and Offset Currents
vs Chip Temperature
TEMPERATURE (°C)
–75
VOLTAGE NOISE (AT 1kHz) (nV/√Hz)
6
7
8
LT1169 • TPC04
5
4
2
0
50
100
3
10
9
–50 –25
25
75
125
V
S
= ±15V
Voltage Noise vs Chip Temperature
TEMPERATURE (°C)
0
INPUT BIAS AND OFFSET CURRENTS (A)
300p
100p
3n
1n
30n
10n
100
LT1169 • TPC05*
30p
10p
3p
1p
0.3p
25
50
75
125
V
S
= ±15V
V
CM
= –10 TO 13V
BIAS
CURRENT
OFFSET
CURRENT
FREQUENCY (Hz)
10
0
POWER SUPPLY REJECTION RATIO (dB)
20
40
60
80
120
100
1k 10k 100k
LT1169 • TPC09
1M 10M
100
T
A
= 25°C
+PSRR
–PSRR
Voltage Gain vs Frequency
FREQUENCY (Hz)
0.01
VOLTAGE GAIN (dB)
100
140
180
1M
LT1169 • TPC10
60
20
–20
1
100
10k
100M
T
A
= 25°C
V
S
= ±15V
CHIP TEMPERATURE (°C)
–75
10
9
8
7
6
5
4
3
2
1
0
–25
50
75
LT1169 • TPC11
–50 25
100
125
0
V
S
= ±15V
V
O
= ±10V, R
L
= 1k
V
O
= ±12V, R
L
= 10k
VOLTAGE GAIN (V/µV)
R
L
=10k
R
L
= 1k
Voltage Gain vs Chip Temperature
FREQUENCY (MHz)
0.1
–10
VOLTAGE GAIN (dB)
PHASE SHIFT (DEG)
30
40
50
1 10 100
LT1169 • TPC12
20
10
0
180
100
80
60
120
140
160
T
A
= 25°C
V
S
= ±15V
C
L
= 10pF
PHASE
GAIN
Gain and Phase Shift
vs Frequency
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency
TEMPERATURE (°C)
–60
COMMON MODE LIMIT (V)
REFERRED TO POWER SUPPLY
V
+
0
–0.5
–1.0
–1.5
–2.0
100
LT1169 • TPC07
3.0
2.0
1.5
2.5
V
–
+1.0
–20
20
60
140
V
+
= 5V TO 20V
V
–
= –5V TO – 20V
FREQUENCY (Hz)
COMMON MODE REJECTION RATIO (dB)
120
100
80
60
40
20
0
1k 100k 1M 10M
LT1169 • TPC08
10k
T
A
= 25°C
V
S
= ±15V
Common Mode Limit
vs Temperature
COMMON MODE RANGE (V)
–15
–10
INPUT BIAS AND OFFSET CURRENTS (pA)
–6
–4
–2
0
2
4
–10
–5
05
LT1169 • TPC06
10
6
8
10
–8
15
T
A
= 25°C
V
S
= ±15V
BIAS CURRENT
OFFSET CURRENT