Datasheet

5
LT1167
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be imparied.
Note 2: Does not include the effect of the external gain resistor R
G
.
Note 3: This parameter is not 100% tested.
Note 4: The LT1167AC/LT1167C are designed, characterized and expected
to meet the industrial temperature limits, but are not tested at –40°C and
85°C. I-grade parts are guaranteed.
Note 5: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
heat sinking and air flow conditions.
Note 6: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25°C, but
the IC is cycled to 85°C I-grade (or 70°C C-grade) or –40°C I-grade
(0°C C-grade) before successive measurement. 60% of the parts will
pass the typical limit on the data sheet.
Note 7: Typical parameters are defined as the 60% of the yield parameter
distribution.
Note 8: Referred to input.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
S
= ±15V, V
CM
= 0V, –40°C ≤ T
A
≤ 85°C, R
L
= 2k, unless otherwise noted. (Note 4)
ELECTRICAL CHARACTERISTICS
LT1167AI LT1167I
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX MIN TYP MAX UNITS
Gain Error G = 1 ● 0.014 0.04 0.015 0.05 %
G = 10 (Note 2)
● 0.130 0.40 0.140 0.42 %
G = 100 (Note 2)
● 0.140 0.40 0.150 0.42 %
G = 1000 (Note 2)
● 0.160 0.40 0.180 0.45 %
G
N
Gain Nonlinearity (Notes 2, 4) V
O
= ±10V, G = 1 ● 2 15 3 20 ppm
V
O
= ±10V, G = 10 and 100 ● 5 20 6 30 ppm
V
O
= ±10V, G = 1000 ● 26 70 30 100 ppm
G/T Gain vs Temperature G < 1000 (Note 2) ● 20 50 20 50 ppm/°C
V
OST
Total Input Referred Offset Voltage V
OST
= V
OSI
+ V
OSO
/G
V
OSI
Input Offset Voltage ● 20 75 25 100 µV
V
OSIH
Input Offset Voltage Hysteresis (Notes 3, 6) 3.0 3.0 µV
V
OSO
Output Offset Voltage ● 180 500 200 600 µV
V
OSOH
Output Offset Voltage Hysteresis (Notes 3, 6) 30 30 µV
V
OSI
/T Input Offset Drift (Note 8) (Note 3) ● 0.05 0.3 0.06 0.4 µV/°C
V
OSO
/T Output Offset Drift (Note 3) ● 0.8 5 1 6 µV/°C
I
OS
Input Offset Current ● 110 550 120 700 pA
I
OS
/T Input Offset Current Drift ● 0.3 0.3 pA/°C
I
B
Input Bias Current ● 180 600 220 800 pA
I
B
/T Input Bias Current Drift ● 0.5 0.6 pA/°C
V
CM
Input Voltage Range V
S
= ±2.3V to ±5V ● –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 V
V
S
= ±5V to ±18V ● –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.1 +V
S
– 1.4 V
CMRR Common Mode Rejection Ratio 1k Source Imbalance,
V
CM
= 0V to ±10V
G = 1
● 86 90 81 90 dB
G = 10
● 98 105 95 105 dB
G = 100
● 114 118 112 118 dB
G = 1000
● 116 133 112 133 dB
PSRR Power Supply Rejection Ratio V
S
= ±2.3V to ±18V
G = 1
● 100 112 95 112 dB
G = 10
● 120 125 115 125 dB
G = 100
● 125 132 120 132 dB
G = 1000
● 128 140 125 140 dB
I
S
Supply Current ● 1.1 1.6 1.1 1.6 mA
V
OUT
Output Voltage Swing V
S
= ±2.3V to ±5V ● –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.4 +V
S
– 1.3 V
V
S
= ±5V to ±18V ● –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 1.6 +V
S
– 1.5 V
I
OUT
Output Current ● 15 20 15 20 mA
SR Slew Rate G = 1, V
OUT
= ±10V ● 0.55 0.95 0.55 0.95 V/µs
V
REF
REF Voltage Range (Note 3) ● –V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V