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LT1122

Fast Settling, JFET Input

Operational Amplifier

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100% Tested Settling Time 340ns Typ

to 1mV at Sum Node, 10V Step 540ns Max

Tested with Fixed Feedback Capacitor

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Slew Rate 60V/µs Min

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Gain Bandwidth Product 14MHz

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Power Bandwidth (20Vp-p) 1.2 MHz

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Unity Gain Stable; Phase Margin 60°

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Input Offset Voltage 600µV Max

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Input Bias Current 25°C 75pA Max

70°C 600pA Max

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Input Offset Current 25°C 40pA Max

70°C 150pA Max

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Low Distortion

ESCRIPTIO

The LT1122 JFET input operational amplifier combines

high speed and precision performance.

A unique poly-gate JFET process minimizes gate series

resistance and gate-to-drain capacitance, facilitating wide

bandwidth performance, without degrading JFET transis-

tor matching.

It slews at 80V/µs and settles in 340ns. The LT1122 is

internally compensated to be unity gain stable, yet it has a

bandwidth of 14MHz at a supply current of only 7mA. Its

speed makes the LT1122 an ideal choice for fast settling

12-bit data conversion and acquisition systems.

The LT1122 offset voltage of 120µV, and voltage gain of

500,000 also support the 12-bit accurate applications.

The input bias current of 10pA and offset current of 4pA

combined with its speed allow the LT1122 to be used in

such applications as high speed sample and hold amplifi-

ers, peak detectors, and integrators.

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Fast 12-Bit D/A Output Amplifiers

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High Speed Buffers

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Fast Sample and Hold Amplifiers

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High Speed Integrators

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Voltage to Frequency Converters

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Active Filters

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Log Amplifiers

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Peak Detectors

12-Bit Voltage Output D/A Converter

Large-Signal Response

5V/DIV

200ns/DIV

AV = –1

1122 TA07

ITY

0mA TO 2mA

OR 4mA

V

0V TO 10V

OUT

12-BIT CURRENT OUTPUT D/A CONVERTER

C = 5pF TO 17pF

(DEPENDING ON D/A CONVERTER USED)

–

LT1122

LT1122•TA01

Summary of content (8 pages)

PAGE 1
LT1122 Fast Settling, JFET Input Operational Amplifier U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 100% Tested Settling Time to 1mV at Sum Node, 10V Step Tested with Fixed Feedback Capacitor Slew Rate Gain Bandwidth Product Power Bandwidth (20Vp-p) Unity Gain Stable; Phase Margin Input Offset Voltage Input Bias Current 25°C 70°C Input Offset Current 25°C 70°C Low Distortion 340ns Typ 540ns Max The LT1122 JFET input operational amplifier combines high speed and precision performance. 60V/µs Min 14MHz 1.
PAGE 2
LT1122 W W W AXI U U ABSOLUTE RATI GS Supply Voltage .................................................... ± 20V Differential Input Voltage ...................................... ± 40V Input Voltage ........................................................ ± 20V Output Short Circuit Duration .......................... Indefinite Lead Temperature (Soldering, 10 sec.)................. 300°C Operating Temperature Range LT1122AM/BM/CM/DM .................... – 55°C to 125°C LT1122AC/BC/CC/DC/CS/DS ........
PAGE 3
LT1122 ELECTRICAL CHARACTERISTICS VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted. LT1122AM/BM LT1122AC/BC MIN TYP MAX SYMBOL PARAMETER CONDITIONS VOUT Output Voltage Swing RL = 2kΩ RL = 600Ω ± 12 ± 12.5 ± 11.5 ± 12 IS Supply Current Minimum Supply voltage (Note 4) ±5 Offset Adjustment Range RPOT ≥ 10k, Wiper to V+ ±4 7.5 LT1122CM/DM LT1122CC/DC LT1122CS/DS MIN TYP MAX ± 12 ± 11.5 10 UNITS ± 12.5 ± 12 7.
PAGE 4
LT1122 ELECTRICAL CHARACTERISTICS VS = ± 15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, unless otherwise noted.
PAGE 5
LT1122 U W TYPICAL PERFOR A CE CHARACTERISTICS Settling Time (Input From 0V to +10V) 1mV/DIV AT SUM NODE 1mV/DIV AT SUM NODE Settling Time (Input From +10V to 0V) 1mV/DIV AT SUM NODE Settling Time (Input From –10V to 0V) 100ns/DIV 100ns/DIV 1122 G01 100ns/DIV 1122 G02 Settling Time (Input From 0V to –10V) 1122 G03 Undistorted Output Swing vs Frequency Large Signal Response PEAK TO PEAK OUTPUT SWING (V) 5V/DIV 1mV/DIV AT SUM NODE 30 200ns/DIV AV = +1 100ns/DIV 1122 G04 1122 G05 VS = ±15V
PAGE 6
LT1122 U W TYPICAL PERFOR A CE CHARACTERISTICS Distribution of Input Offset Voltage Input Bias and Offset Currents Over Temperature 400 200 0 –900 30K INPUT BIAS AND OFFSET CURRENT (pA) 600 VS = ±15V TA = 25°C (NOT WARMED UP) INPUT BIAS AND OFFSET CURRENTS (pA) 3370 UNITS TESTED IN ALL PACKAGES NUMBER OF UNITS 120 100K 800 VS = ±15V VCM = 0V 10K 3K BIAS CURRENT 1K 300 100 30 OFFSET CURRENT 10 3 1 –100 100 –500 25 0 900 500 INPUT OFFSET VOLTAGE (µV) 50 75 VS = ±15V TA = 25°C (
PAGE 7
LT1122 U W U UO APPLICATI S I FOR ATIO Settling Time Measurements Settling time test circuits shown on some competitive devices’ data sheets require: 1. A “flat top” pulse generator. Unfortunately, flat top pulse generators are not commercially available. 2. A variable feedback capacitor around the device under test. This capacitor varies over a four to one range.
PAGE 8
LT1122 U TYPICAL APPLICATIONS Quartz Stabilized Oscillator With 9ppm Distortion OUTPUT –15V 4.7k LT1004 2.5V 47k 4kHz J CUT 5k OUTPUT AMPLITUDE 10 µ F TRIM + 4.7k +15V + 4.