Datasheet
12
LT1113
1113fb
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Typical performance of the instrumentation amplifier:
Input offset voltage = 0.8mV
Input bias current = 320pA
Input offset current = 10pA
Input resistance = 10
11
Ω
Input noise = 3.4µV
P-P
High Speed Operation
The low noise performance of the LT1113 was achieved by
making the input JFET differential pair large to maximize
the first stage gain. Increasing the JFET geometry also
increases the parasitic gate capacitance, which if left
unchecked, can result in increased overshoot and ringing.
When the feedback around the op amp is resistive (R
F
),
a pole will be created with R
F
, the source resistance and
capacitance (R
S
,C
S
), and the amplifier input capacitance
(C
IN
= 27pF). In closed loop gain configurations and
with R
S
and R
F
in the kilohm range (Figure 5), this pole
can create excess phase shift and even oscillation.
A small capacitor (C
F
) in parallel with R
F
eliminates this
problem. With R
S
(C
S
+ C
IN
) = R
F
C
F
, the effect of the
feedback pole is completely removed.
Figure 5.
The concepts of common mode and power supply
rejection ratio match (∆CMRR and ∆PSRR) are best
demonstrated with a numerical example:
Assume CMRR
A
= +50µV/V or 86dB,
and CMRR
B
= + 39µV/V or 88dB,
then ∆CMRR = 11µV/V or 99dB;
if CMRR
B
= -39µV/V which is still 88dB,
then ∆CMRR = 89µV/V or 81dB
Clearly the LT1113, by specifying and guaranteeing all of
these matching parameters, can significantly improve the
performance of matching-dependent circuits.
Figure 4. Three Op Amp Instrumentation Amplifier
4
OUTPUT
C1
50pF
R7
10k
R6
10k
1113 • F04
GAIN =
BANDWIDTH =
INPUT REFERRED NOISE =
WIDEBAND NOISE DC TO 400kHz =
C
L
≤
100
400kHz
6.6nV/√Hz AT 1kHz
6.6 µV
RMS
0.01µF
IN
–
15V
8
1
–15V
–
+
–
+
1/2
LT1113
IC1
1/2
LT1113
IC1
IN
+
R3
1k
R2
200Ω
R1
1k
7
6
5
3
2
R4
1k
1
2
C
L
3
–
+
1/2
LT1113
IC2
R5
1k
–
+
1113 • F05
OUTPUT
R
F
R
S
C
S
C
IN
C
F