Datasheet

5
LT1055/LT1056
10556fc
For MIL-STD components, please refer to LTC883 data sheet for test
listing and parameters.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power; (b) at T
A
= 25°C
only, with the chip heated to approximately 38°C for the LT1055 and to
45°C for the LT1056, to account for chip temperature rise when the device
is fully warmed up.
Note 3: 10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
Note 4: This parameter is tested on a sample basis only.
Note 5: Current noise is calculated from the formula: i
n
= (2ql
B
)
1/2
, where
q = 1.6 • 10
–19
coulomb. The noise of source resistors up to 1GΩ swamps
the contribution of current noise.
Note 6: Offset voltage drift with temperature is practically unchanged
when the offset voltage is trimmed to zero with a 100k potentiometer
between the balance terminals and the wiper tied to V
+
. Devices tested to
tighter drift specifications are available on request.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the temperature range
0°C ≤ T
A
≤ 70°C. V
S
= ±15V, V
CM
= 0V, unless otherwise noted.
LT1055CS8/LT1056CS8
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage (Note 2) ● 800 2200 µV
Average Temperature Coefficient of Input Offset Voltage ● 415µV/°C
I
OS
Input Offset Current Warmed Up, T
A
= 70°C ● 18 150 pA
I
B
Input Bias Current Warmed Up, T
A
= 70°C ● ±60 ±400 pA
A
VOL
Large-Signal Voltage Gain V
O
= ±10V, R
L
= 2k ● 60 250 V/mV
CMRR Common Mode Rejection Ratio V
CM
= ±10.5V ● 82 98 dB
PSRR Power Supply Rejection Ratio V
S
= ±10V to ±18V ● 87 103 dB
V
OUT
Output Voltage Swing R
L
= 2K ● ±12 ±13.1 V