Datasheet

3
LT1055/LT1056
LT1055AM LT1055M
LT1056AM LT1056M
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
OS
Input Offset Voltage (Note1) LT1055 ● — 180 500 — 250 1200 µV
LT1056 ● — 180 550 — 250 1250 µV
Average Temperature (Note 5)
● — 1.3 4.0 — 1.8 8.0 µV/°C
Coefficient of Input Offset
Voltage
I
OS
Input Offset Current Warmed Up LT1055 ● — 0.20 1.2 — 0.25 1.8 nA
T
A
= 125°C LT1056 ● — 0.25 1.5 — 0.30 2.4 nA
I
B
Input Bias Current Warmed Up LT1055 ● — ±0.4 ±2.5 — ±0.5 ±4.0 nA
T
A
= 125°C LT1056 ● — ±0.5 ±3.0 — ±0.6 ±5.0 nA
A
VOL
Large-Signal Voltage Gain V
O
= ±10V, R
L
= 2k ● 40 120 — 35 120 — V/mV
CMRR Common-Mode Rejection Ratio V
CM
= ±10.5V ● 85100—8298— dB
PSRR Power Supply Rejection Ratio V
S
= ±10V to ±17V ● 88 104 — 86 102 — dB
V
OUT
Output Voltage Swing R
L
= 2k ● ±12 ±12.9 — ±12 ±12.9 — V
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
OS
Input Offset Voltage (Note1) LT1055 H Package ● — 100 330 — 140 750 µV
LT1056 H Package
● — 100 360 — 140 800 µV
LT1055 N8 Package
● — — — — 250 1250 µV
LT1056 N8 Package ● — — — — 280 1350 µV
Average Temperature H Package (Note 5) ● — 1.2 4.0 — 1.6 8.0 µV/°C
Coefficient of Input Offset N8 Package (Note 5)
● — — — — 3.0 12.0 µV/°C
Voltage
I
OS
Input Offset Current Warmed Up LT1055 ● —1050 — 1680 pA
T
A
= 70°C LT1056 ● —1470—18100 pA
I
B
Input Bias Current Warmed Up LT1055 ● — ±30 ±150 — ±40 ±200 pA
T
A
= 70°C LT1056 ● — ±40 ±80 — ±50 ±240 pA
A
VOL
Large-Signal Voltage Gain V
O
= ±10V, R
L
= 2k ● 80 250 — 60 250 — V/mV
CMRR Common-Mode Rejection Ratio V
Cm
= ±10.5V ● 85100—8298— dB
PSRR Power Supply Rejection Ratio V
S
= ±10V to ±18V ● 89 105 — 87 103 — dB
V
OUT
Output Voltage Swing R
L
= 2k ● ±12 ±13.1 — ±12 ±13.1 — V
LT1055AC
LT1056AC
V
S
= ±15V, V
CM
= 0V, –55°C ≤ T
A
≤ 125°C unless otherwise noted.
The ● denotes specifications which apply over the full operating
temperature range.
For MIL-STD components, please refer to LTC883 data sheet for test
listing and parameters.
Note 1: Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power; (b) at T
A
= 25°C
only, with the chip heated to approximately 38°C for the LT1055 and to
45°C for the LT1056, to account for chip temperature rise when the device
is fully warmed up.
Note 2: 10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
Note 3: This parameter is tested on a sample basis only.
Note 4: Current noise is calculated from the formula: i
n
= (2ql
B
)
1/2
, where
q = 1.6 × 10
–19
coulomb. The noise of source resistors up to 1GΩ
swamps the contribution of current noise.
Note 5: Offset voltage drift with temperature is practically unchanged when
the offset voltage is trimmed to zero with a 100k potentiometer between
the balance terminals and the wiper tied to V
+
. Devices tested to tighter
drift specifications are available on request.
LT1055CH/LT1056CH
LT1055CN8/LT1056CN8
V
S
= ±15V, V
CM
= 0V, 0°C ≤ T
A
≤ 70°C unless otherwise noted.