Datasheet

6
LT1054
PIN FUNCTIONS
UUU
OSC (Pin 7): Oscillator Pin. This pin can be used to raise or
lower the oscillator frequency or to synchronize the device
to an external clock. Internally pin 7 is connected to the
oscillator timing capacitor (C
t
≈ 150pF) which is alternately
charged and discharged by current sources of ±7µA so that
the duty cycle is ≈50%. The LT1054 oscillator is designed
to run in the frequency band where switching losses are
minimized. However the frequency can be raised, lowered,
or synchronized to an external system clock if necessary.
The frequency can be lowered by adding an external
capacitor (C1, Figure 2) from pin 7 to ground. This will
increase the charge and discharge times which lowers the
oscillator frequency. The frequency can be increased by
adding an external capacitor (C2, Figure 2, in the range of
5pF to 20pF) from pin 2 to pin 7. This capacitor will couple
charge into C
t
at the switch transitions, which will shorten
the charge and discharge time, raising the oscillator fre-
quency. Synchronization can be accomplished by adding
an external resistive pull-up from pin 7 to the reference pin
(pin 6). A 20k pull-up is recommended. An open collector
gate or an NPN transistor can then be used to drive the
oscillator pin at the external clock frequency as shown in
Figure 2. Pulling up pin 7 to an external voltage is
not recommended. For circuits that require both fre-
quency synchronization and regulation, an external refer-
ence can be used as the reference point for the top of the
R1/R2 divider allowing pin 6 to be used as a pull-up point
for pin 7.
FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has
two functions. Pulling pin 1 below the shutdown threshold
(≈0.45V) puts the device into shutdown. In shutdown the
reference/regulator is turned off and switching stops. The
switches are set such that both C
IN
and C
OUT
are dis-
charged through the output load. Quiescent current in
shutdown drops to approximately 100µA (see Typical
Performance Characteristics). Any open-collector gate can
be used to put the LT1054 into shutdown. For normal
(unregulated) operation the device will start back up when
the external gate is shut off. In LT1054 circuits that use the
regulation feature, the external resistor divider can provide
enough pull-down to keep the device in shutdown until the
output capacitor (C
OUT
) has fully discharged. For most
applications where the LT1054 would be run intermittently,
this does not present a problem because the discharge time
of the output capacitor will be short compared to the off-
time of the device. In applications where the device has to
start up before the output capacitor (C
OUT
) has fully dis-
charged, a restart pulse must be applied to pin 1 of the
LT1054. Using the circuit of Figure 5, the restart signal can
be either a pulse (t
p
> 100µs) or a logic high. Diode coupling
the restart signal into pin 1 will allow the output voltage to
come up and regulate without overshoot. The resistor
divider R3/R4 in Figure 5 should be chosen to provide a
signal level at pin 1 of 0.7V to 1.1V.
Pin 1 is also the inverting input of the LT1054’s error
amplifier and as such can be used to obtain a regulated
output voltage.Figure 2
V
IN
C
OUT
C
IN
C2
+
+
C1
LT1054 • F02
LT1054
FB/SHDN
CAP
+
GND
CAP
–
V
+
OSC
V
REF
V
OUT