Datasheet

LT1016
3
1016fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 5V, V
OUT
(Q) = 1.4V, V
LATCH
= 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LT1016C/I
UNITSMIN TYP MAX
V
OS
Input Offset Voltage R
S
≤ 100Ω (Note 2)
●
1.0 ±3
3.5
mV
mV
∆V
OS
/∆T Input Offset Voltage Drift
●
4 µV/°C
I
OS
Input Offset Current (Note 2)
●
0.3
0.3
1.0
1.3
µA
µA
I
B
Input Bias Current (Note 3)
●
5 10
13
µA
µA
Input V
oltage Range (Note 6)
Single 5V Supply
●
●
–3.75
1.25
3.5
3.5
V
V
CMRR Common Mode Rejection
–3.75V ≤ V
CM
≤ 3.5V
●
80 96 dB
PSRR Supply Voltage Rejection Positive Supply 4.6V ≤ V
+
≤ 5.4V
LT1016C
●
60 75 dB
Positive Supply 4.6V ≤ V
+
≤ 5.4V
LT1016I
●
54 75 dB
Negative Supply 2V ≤ V
–
≤ 7V
●
80 100 dB
A
V
Small-Signal Voltage Gain 1V ≤ V
OUT
≤ 2V 1400 3000 V/V
V
OH
Output High Voltage V
+
≥ 4.6V I
OUT
=1mA
I
OUT
= 10mA
●
●
2.7
2.4
3.4
3.0
V
V
V
OL
Output Low Voltage I
SINK
= 4mA
I
SINK
= 10mA
●
0.3
0.4
0.5 V
V
I
+
Positive Supply Current
●
25 35 mA
I
–
Negative Supply Current
●
3 5 mA
V
IH
LATCH Pin Hi Input Voltage
●
2.0 V
V
IL
LATCH Pin Lo Input Voltage
●
0.8 V
I
IL
LATCH Pin Current V
LATCH
= 0V
●
500 µA
t
PD
Propagation Delay (Note 4) ∆V
IN
= 100mV, OD = 5mV
●
10 14
16
ns
ns
∆V
IN
= 100mV, OD = 20mV
●
9 12
15
ns
ns
∆t
PD
Differential Propagation Delay (Note 4) ∆V
IN
= 100mV,
OD = 5mV
3 ns
Latch Setup T
ime 2 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (I
B
) is defined as the average of the two input
currents.
Note 4: t
PD
and ∆t
PD
cannot be measured in automatic handling equipment
with low values of overdrive. The LT1016 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that t
PD
and ∆t
PD
limits shown can be guaranteed with this test if additional DC tests are
performed to guarantee that all internal bias conditions are correct. For low
overdrive conditions V
OS
is added to overdrive. Differential propogation
delay is defined as: ∆t
PD
= t
PDLH
– t
PDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This
parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.