Datasheet

LT1016
3
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (I
B
) is defined as the average of the two input
currents.
Note 4: t
PD
and Dt
PD
cannot be measured in automatic handling
equipment with low values of overdrive. The LT1016 is sample tested with
a 1V step and 500mV overdrive. Correlation tests have shown that t
PD
and
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25∞C. V
+
= 5V, V
–
= 5V, V
OUT
(Q) = 1.4V, V
LATCH
= 0V, unless otherwise noted.
LT1016C/I
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage R
S
£ 100W (Note 2) 1.0 ±3mV
● 3.5 mV
DV
OS
Input Offset Voltage Drift ● 4 mV/∞C
DT
I
OS
Input Offset Current (Note 2) 0.3 1.0 mA
● 0.3 1.3 mA
I
B
Input Bias Current (Note 3) 5 10 mA
● 13 mA
Input Voltage Range (Note 6) ● –3.75 3.5 V
Single 5V Supply
● 1.25 3.5 V
CMRR Common Mode Rejection –3.75V £ V
CM
£ 3.5V ● 80 96 dB
PSRR Supply Voltage Rejection Positive Supply 4.6V £ V
+
£ 5.4V ● 60 75 dB
LT1016C
Positive Supply 4.6V £ V
+
£ 5.4V ● 54 75 dB
LT1016I
Negative Supply 2V £ V
–
£ 7V ● 80 100 dB
A
V
Small-Signal Voltage Gain 1V £ V
OUT
£ 2V 1400 3000 V/V
V
OH
Output High Voltage V
+
≥ 4.6V I
OUT
=1mA ● 2.7 3.4 V
I
OUT
= 10mA ● 2.4 3.0 V
V
OL
Output Low Voltage I
SINK
= 4mA ● 0.3 0.5 V
I
SINK
= 10mA 0.4 V
I
+
Positive Supply Current ● 25 35 mA
I
–
Negative Supply Current ● 35 mA
V
IH
LATCH Pin Hi Input Voltage ● 2.0 V
V
IL
LATCH Pin Lo Input Voltage ● 0.8 V
I
IL
LATCH Pin Current V
LATCH
= 0V ● 500 mA
t
PD
Propagation Delay (Note 4) DV
IN
= 100mV, OD = 5mV 10 14 ns
● 16 ns
DV
IN
= 100mV, OD = 20mV 9 12 ns
● 15 ns
Dt
PD
Differential Propagation (Note 4) DV
IN
= 100mV, 3 ns
Delay OD = 5mV
Latch Setup Time 2ns
Dt
PD
limits shown can be guaranteed with this test if additional DC tests
are performed to guarantee that all internal bias conditions are correct. For
low overdrive conditions V
OS
is added to overdrive. Differential
propogation delay is defined as: Dt
PD
= t
PDLH
– t
PDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.