Datasheet

LTC2442
24
2442fa
For more information www.linear.com/LTC2442
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC
4
digital filter and
the digital and analog autocalibration circuits determines
the LTC2442 input bandwidth and rejection characteristics.
The digital filter’s response can be adjusted by setting
the oversample ratio (OSR) through the SPI interface or
by supplying an external conversion clock to the f
O
pin.
Table 7 lists the properties of the LTC2442 with various
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fine tuning
the characteristics of the LTC2442 to the application.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
This is the first notch in the SINC
4
portion of the digital filter
and depends on the fo clock frequency and the oversample
ratio. Rejection at this frequency and its multiples (up to
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Effective Noise Bandwidth
The LTC2442 has extremely good input noise rejection from
the first notch frequency all the way out to the modulator
sample rate (typically 1.8MHz). Effective noise bandwidth
is a measure of how the ADC will
reject wideband input
noise up to the modulator sample rate.
Table 7
Over-
sample
Ratio
(OSR)
*RMS
Noise
ENOB
(V
REF
= 5V)
Maximum
Conversion Rate
First Notch
Frequency
Effective
Noise BW
–3dB
point (Hz)
Internal
9MHz clock
External
f
0
Internal
9MHz clock
External
f
0
Internal
9MHz clock
External
f
0
Internal
9MHz clock
External
f
0
64 23µV 17.7 3515.6 f
0
/2560 28125 f
0
/320 3148 f
0
/5710 1696 f
0
/5310
128 3.6µV 20.4 1757.8 f
0
/5120 14062.5 f
0
/640 1574 f
0
/2860 848 f
0
/10600
256 2.1µV 21.2 878.9 f
0
/10240 7031.3 f
0
/1280 787 f
0
/1140 424 f
0
/21200
512 1.5µV 21.6 439.5 f
0
/20480 3515.6 f
0
/2560 394 f
0
/2280 212 f
0
/42500
1024 1.2µV 22 219.7 f
0
/40960 1757.8 f
0
/5120 197 f
0
/4570 106 f
0
/84900
2048 840nV 22.5 109.9 f
0
/81920 878.9 f
0
/1020 98.4 f
0
/9140 53 f
0
/170000
4096 630nV 22.4 54.9 f
0
/163840 439.5 f
0
/2050 49.2 f
0
/18300 26.5 f
0
/340000
8192 430nV 23.5 27.5 f
0
/327680 219.7 f
0
/4100 24.6 f
0
/36600 13.2 f
0
/679000
16384 305nV 24 13.7 f
0
/655360 109.9 f
0
/8190 12.4 f
0
/73100 6.6 f
0
/1358000
32768 220nV 24.4 6.9 f
0
/1310720 54.9 f
0
/16380 6.2 f
0
/146300 3.3 f
0
/2717000
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 64 include effects
from internal modulator quantization noise.
29 2
30
1
36
6
7
35
3
2442 F14
34
4,5,32
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT
–0.5V
REF
TO
0.5V
REF
3-WIRE
SPI INTERFACE
4.5V TO 5.5V
31
V
CC
BUSY
F
O
REF
+
SCK
CH0
CH1
SDO
GND
CS
EXT
LTC2442
REF
–
1µF
0.1µF
LTC1799
OUT
DIV SET
GND
V
+
R
SET
NC
•
•
•
Figure 14. Simple External Clock Source
applications inForMation