Datasheet

LTC2442
17
2442fa
For more information www.linear.com/LTC2442
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and immedi
-
ately initiates a new conversion. Thirteen serial input data
bits are required in order to properly program the speed/
resolution and input channel. If the data output sequence
is aborted prior to the 13th rising edge of SCK, the new
input data is ignored, and the previously selected speed/
resolution and channel are used for the next conversion
cycle. This is useful for systems not requiring all 32 bits
of output data, aborting an invalid conversion cycle or
synchronizing the start of a conversion. If a new channel
is being programmed, the rising edge of CS must come
after the 14th falling edge of SCK in order to store the
data input sequence.
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
1 2 3 4 5 6 1 5
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
2442 F05
CONVERSION
SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE
DON'T CARE
V
CC
V
+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
F
O
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1µF
0.1µF
4.5V TO 5.5V V
CC
TO 15V
LTC2442
1µF
0.1µF
CS
–15V TO GND
V
–
REF
+
REF
–
OUTB
–INB
ADCINB
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
OUTA
–INA
ADCINA
4-WIRE
SPI INTERFACE
Figure 5. External Serial Clock, Reduced Output Data Length
applications inForMation