Datasheet

LTC2442
10
2442fa
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sult is shifted out on the serial data out pin (SDO) under
the control of the serial clock (SCK). Data is updated on
the falling edge of SCK allowing the user to reliably latch
data on the rising edge of SCK (see Figure 3). The data
output state is concluded once 32 bits are read out of the
ADC or when CS is brought HIGH. In either scenario, the
device automatically initiates a new conversion and the
cycle repeats.
Through timing control of the CS, SCK and EXT pins,
the LTC2442 offers several flexible modes of operation
(internal or external SCK). These various modes do not
require programming configuration registers; moreover,
they do not disturb the cyclic operation described above.
These modes of operation are described in detail in the
Serial Interface Timing Modes section.
Ease of Use
The LTC2442 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle while operating in the 1X mode. There is a one-to-one
correspondence between the conversion and the output
data. Therefore, multiplexing multiple analog voltages is
easy. Speed/resolution adjustments may be made seam
-
lessly between two conversions without settling errors.
The LTC2442 performs
offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2442 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approx-
imately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selection.
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The
POR signal clears all internal registers. The conversion
immediately following a POR is performed on the input
channel SEL
+
= CH0, SEL
–
= CH1 at an OSR = 256 in the
1X mode. Following the POR signal, the LTC2442 starts
a normal conversion cycle and follows the succession
of states described above. The first conversion result
following POR is accurate within the specifications of the
device if the power supply voltage is restored within the
operating range (4.5V to 5.5V) before the end of the POR
time interval
.
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
Hi-Z
2442 F03
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
applications inForMation