Datasheet

LTC2483
21
2483fc
In addition to this gain error, the converter INL per-
formance is degraded by the reference source imped-
ance. The INL is caused by the input dependent terms
–V
IN
2
/(V
REF
• R
EQ
) – (0.5 • V
REF
• D
T
)/R
EQ
in the reference
pin current as expressed in Figure 7. When using internal
oscillator, every 100Ω of reference source resistance
translates into about 0.61ppm additional INL error. When
CA0/F
0
is driven by an external oscillator with a frequency
f
EOSC
, every 100Ω of source resistance driving REF
+
or
REF
–
translates into about 2.18 • 10
–6
• f
EOSC
ppm ad-
ditional INL error. Figure 15 shows the typical INL error
due to the source resistance driving the REF
+
or REF
–
pins
when large C
REF
values are used. The user is advised to
minimize the source impedance driving the REF
+
and
REF
–
pins.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
– V
INCM
) and a 5V reference,
each ohm of reference source resistance introduces an
extra (V
REFCM
– V
INCM
)/(V
REF
• R
EQ
) full-scale gain error,
which is 0.067ppm when using internal oscillator. If an
applicaTions inFormaTion
external clock is used, the corresponding extra gain error
is 0.24 • 10
–6
• f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF
+
and REF
–
, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Figure 15. INL vs Differential Input Voltage and
Reference Source Resistance for C
REF
> 1µF
V
IN
/V
REF
(V)
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2483 F15
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25°C
C
REF
= 10µF
R = 1k
R = 100Ω
R = 500Ω