Datasheet

LTC2483
15
2483fc
Frequency Rejection Selection (CA0/F
0
)
The LTC2483 internal oscillator provides better than 87dB
normal mode rejection at line frequencies of 50Hz and
60Hz and all of their harmonics (up to the 255th) from
48Hz to 62.4Hz.
When a fundamental rejection frequency different from
50Hz/60Hz is required or when the converter must be
synchronized with an outside source, the LTC2483 can
operate with an external conversion clock. The converter
applicaTions inFormaTion
automatically detects the presence of an external clock
signal at the CA0/F
0
pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency f
EOSC
of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the HIGH and LOW periods t
HEO
and
t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2483 provides better than 110dB
SLEEP DATA OUTPUT
START BY
MASTER
ACK BY
LTC2483
ACK BY
MASTER
NACK BY
MASTER
LSBR MSBSGN D15
7 … …8 9 1 2 9
1 2 3 4 5 6 7 8 9
1
7-BIT
ADDRESS
2483 F03
Figure 3. Timing Diagram for Reading from the LTC2483
S ACK DATA Sr DATA TRANSFERRING P
SLEEP DATA INPUT/OUTPUT CONVERSION
7-BIT ADDRESS
R/W
2483 F04
Figure 4. The LTC2483 Conversion Sequence
7-BIT ADDRESS
CONVERSION CONVERSION
CONVERSION
SLEEP SLEEPDATA OUTPUT DATA OUTPUT
7-BIT ADDRESSS SR RACK ACKREAD READP P
2483 F05
Figure 5. Consecutive Reading at the Same Configuration