Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsDev KitsPCB design board

LTC2483

2483fc

Typical applicaTion

DescripTion

16-Bit ∆Σ ADC with Easy Drive

Input Current Cancellation

and I

C Interface

The LTC

2483 combines a 16-bit plus sign No Latency

∆∑™ analog-to-digital converter with patented Easy Drive

technology and I

C digital interface. The patented sampling

scheme eliminates dynamic input current errors and the

shortcomings of on-chip buffering through automatic

cancellation of differential input current. This allows large

external source impedances and input signals, with rail-to-

rail input range to be directly digitized while maintaining

exceptional DC accuracy.

The LTC2483 allows a wide common mode input range

(0V to V

) independent of the reference voltage. The

reference can be as low as 100mV or can be tied directly

to V

. The noise level is 600nV

RMS

independent of V

REF

This allows direct digitization of low level signals with

16-bit accuracy. The LTC2483 includes an on-chip trimmed

oscillator, eliminating the need for external crystals or

oscillators and provides 87dB rejection of 50Hz and 60Hz

line frequency noise. Absolute accuracy and low drift are

automatically maintained through continuous, transparent,

offset and full-scale calibration.

+FS Error vs R

SOURCE

at IN

and IN

–

FeaTures

applicaTions

Easy Drive™ Technology Enables Rail-to-Rail

Inputs with Zero Differential Input Current

Directly Digitizes High Impedance Sensors with

Full Accuracy

600nV

RMS

Noise, Independent of V

REF

GND to V

Input/Reference Common Mode Range

2-Wire I

C Interface

Simultaneous 50Hz/60Hz Rejection

2ppm (0.25 LSB) INL, No Missing Codes

1ppm Offset and 15ppm Full-Scale Error

No Latency: Digital Filter Settles in a Single Cycle

Single Supply 2.7V to 5.5V Operation

Internal Oscillator

Six Addresses Available

Available in a Tiny (3mm × 3mm) 10-Lead

DFN Package

Direct Sensor Digitizer

Weight Scales

Direct Temperature Measurement

Strain Gauge Transducers

Instrumentation

Industrial Process Control

DVMs and Meters

LTC2483

REF

GND

–

1µF

SDA

2-WIRE

C INTERFACE

0.1µF

10k

DIFF

= 0

10k

0.1µF

CA0/F

2483 TA01

CA1

SCL

6 ADDRESSES

REF

–

SENSE

SOURCE

(Ω)

+FS ERROR (ppm)

–20

100k

–40

–60

–80

10 100 10k

= 5V

REF

= 5V

= 3.75V

–

= 1.25V

= GND

= 25°C

= 1µF

2483 TA02

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Patents pending.

Summary of content (34 pages)

PAGE 1
LTC2483 16-Bit ∆Σ ADC with Easy Drive Input Current Cancellation and I2C Interface Description Features n n n n n n n n n n n n n Easy Drive™ Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nVRMS Noise, Independent of VREF GND to VCC Input/Reference Common Mode Range 2-Wire I2C Interface Simultaneous 50Hz/60Hz Rejection 2ppm (0.
PAGE 2
LTC2483 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltage (VCC) to GND........................– 0.3V to 6V Analog Input Voltage to GND........ – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND...... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2483C................................................. 0°C to 70°C LTC2483I . .....................................
PAGE 3
LTC2483 converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN – = IN+ ≤ VCC (Note 5) l MIN 140 TYP MAX UNITS dB Input Common Mode Rejection 50Hz ± 2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN – = IN+ ≤ VCC (Note 5) l 140 dB Input Common Mode Rejection 60Hz ±2% 2.
PAGE 4
LTC2483 I2C DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage l VIL Low Level Input Voltage l 0.3VCC V VIL(CA1) Low Level Input Voltage for Address Pin l 0.
PAGE 5
LTC2483 timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN fEOSC External Oscillator Frequency Range l tHEO External Oscillator High Period l tLEO External Oscillator Low Period l tCONV_1 Conversion Time l l 144.1 Simultaneous 50Hz/60Hz External Oscillator (Note 10) TYP MAX UNITS 10 4000 kHz 0.125 100 µs 0.125 100 µs 149.
PAGE 6
LTC2483 Typical Performance Characteristics Integral Nonlinearity (VCC = 5V, VREF = 5V) –45°C 1 25°C 0 85°C –1 –2 3 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V 2 INL (ppm OF VREF) 2 1 –45°C, 25°C, 90°C 0 –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 12 4 0 85°C –4 –8 4 –45°C 0 –4 2 –12 –1.25 2.5 Noise Histogram (6.8sps) 4 12 12 NUMBER OF READINGS (%) 8 6 4 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) –4 –12 –1.25 1.
PAGE 7
LTC2483 Typical Performance Characteristics RMS Noise vs Input Differential Voltage VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0.8 0.7 0.6 RMS Noise vs Temperature (TA) 1.0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND TA = 25°C 0.9 0.8 RMS NOISE (µV) RMS NOISE (ppm OF VREF) 0.9 RMS Noise vs VIN(CM) 1.0 0.7 0.6 0.5 0.4 2.5 –1 0 2 1 3 5 4 OFFSET ERROR (ppm OF VREF) 0.8 RMS NOISE (µV) RMS NOISE (µV) 0.6 0.7 0.6 0.5 0.5 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 0.4 5.
PAGE 8
LTC2483 Typical Performance Characteristics On-Chip Oscillator Frequency vs Temperature 310 310 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND 300 –45 –30 –15 75 306 304 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 –80 –60 –80 –100 –100 –120 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) –140 30600 30650 30700 500 1.8 VREF = VCC IN+ = GND IN– = GND CA0/F0 = EXT OSC TA = 25°C 450 1.6 SUPPLY CURRENT (µA) SLEEP MODE CURRENT (µA) VCC = 5V 160 VCC = 2.
PAGE 9
LTC2483 Pin Functions REF+ (Pin 1), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is more positive than the reference negative input, REF –, by at least 0.1V. SDA (Pin 7): Serial Data Output Line of the I2C Interface. In the transmitter mode (read), the conversion result is output through the SDA pin.
PAGE 10
LTC2483 functional Block Diagram 2 1 4 5 VCC REF+ IN+ IN– IN– SCL REF+ IN+ I2C 3RD ORDER ∆∑ ADC SERIAL INTERFACE REF – SDA CA1 CA0/F0 6 7 9 10 AUTOCALIBRATION AND CONTROL REF – 3 GND 8 INTERNAL OSCILLATOR 2483 FB 2483fc 10
PAGE 11
LTC2483 Applications Information Converter Operation Converter Operation Cycle The LTC2483 is a low power, ∆∑ analog-to-digital converter with an I2C interface. After power-on reset, its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). POWER-ON RESET CONVERSION SLEEP NO ACKNOWLEDGE YES DATA OUTPUT NO STOP OR READ 24 BITS YES 2483 F01 Figure 1.
PAGE 12
LTC2483 Applications Information The START and STOP Conditions Data Transferring A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free again a certain time after the STOP condition. START and STOP conditions are always generated by the master.
PAGE 13
LTC2483 Applications Information LTC2483 Data Format After a START condition, the master sends a 7-bit address followed by a R/W bit. The bit R/W is 1 for a read request and 0 for a write request. If the 7-bit address agrees with an LTC2483’s address, that device is selected. When the device is in the conversion state, it does not accept the request and issues a not-acknowledge (NACK) by leaving SDA HIGH. A write operation will also generate an NACK signal.
PAGE 14
LTC2483 Applications Information Initiating a New Conversion Easy Drive Input Current Cancellation When the LTC2483 finishes a conversion, it automatically enters the sleep state. Once in the sleep state, the device is ready for a read operation. After the device acknowledges a read request, the device exits the sleep state and enters the data output state.
PAGE 15
LTC2483 Applications Information Frequency Rejection Selection (CA0/F0) automatically detects the presence of an external clock signal at the CA0/F0 pin and turns off the internal oscillator. The chip address for CA0 is internally set HIGH. The frequency fEOSC of the external signal must be at least 10kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the HIGH and LOW periods tHEO and tLEO are observed.
PAGE 16
LTC2483 Applications Information normal mode rejection in a frequency range of fEOSC/5120 ± 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/5120 is shown in Figure 6. – 80 NORMAL MODE REJECTION (dB) – 85 – 90 Ease of Use The LTC2483 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data.
PAGE 17
LTC2483 Applications Information the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. Since the transition noise (600nV) is much less than the quantization noise (VREF/217), a decrease in the reference voltage will increase the converter resolution.
PAGE 18
LTC2483 Applications Information Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10kΩ with no external bypass capacitor or up to 500Ω with 0.001µF bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization of the sensor is possible.
PAGE 19
LTC2483 Applications Information is zero, the common mode input current (IIN++ IIN–)/2 is proportional to the difference between the common mode input voltage (VINCM) and the common mode reference voltage (VREFCM). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. The accuracy of the converter is unaffected by settling errors.
PAGE 20
LTC2483 Applications Information gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same.
PAGE 21
LTC2483 Applications Information In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms –VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference pin current as expressed in Figure 7. When using internal oscillator, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error.
PAGE 22
LTC2483 Applications Information Output Data Rate When using its internal oscillator, the LTC2483 produces up to 6.82sps with simultaneous 50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (CA0/F0 connected to an external oscillator), the LTC2483 output data rate can be increased as desired.
PAGE 23
LTC2483 Applications Information Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC.
PAGE 24
LTC2483 Applications Information Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2483 input bandwidth. When the internal oscillator is used, the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the CA0/F0 pin, the 3dB input bandwidth is 11.8 • 10–6 • fEOSC.
PAGE 25
LTC2483 Applications Information 100 –1 60Hz fEOSC = 307.2kHz –2 50Hz fEOSC = 256kHz –3 –4 INTERNAL OSCILLATOR –5 –6 INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) INPUT SIGNAL ATTENUATION (dB) 0 10 1 0.1 0.1 1 3 0 4 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2483 F24 Figure 25. Input Refered Noise Equivalent Bandwidth of an Input Connected White Noise Source 0 0 –10 –10 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) Figure 24.
PAGE 26
LTC2483 Applications Information The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 30, 31 and 32. Typical measured values of the normal mode rejection of the LTC2483 operating with an external oscillator and a 60Hz notch setting are shown in Figure 30 superimposed over the theoretical calculated curve.
PAGE 27
LTC2483 Applications Information MEASURED DATA CALCULATED DATA –20 –40 VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C –60 –80 –100 –120 0 15 30 45 60 75 0 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION (dB) 0 –40 –80 –100 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2483 F30 2483 F31 Figure 30. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (60Hz Notch fEOSC = 307.
PAGE 28
LTC2483 applications information /* LTC248X.h Processor setup and Lots of useful defines for configuring the LTC2481, LTC2483, and LTC2485. */ #include <16F73.h> // Device #use delay(clock=6000000) // 6MHz clock //#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Configuration fuses #rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config. #use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port #include “PCM73A.h” // Various defines #include “lcd.
PAGE 29
LTC2483 applications information /* LTC2483.c Basic voltmeter test program for LTC2483 Reads LTC2483, converts result to volts, and prints voltage to a 2 line by 16 character LCD display. Mark Thoren Linear Technology Corporation June 23, 2005 Written for CCS PCM compiler, Version 3.182 */ #include “LTC248X.h” /*** read_LTC2483() ************************************************************ This is the function that actually does all the work of talking to the LTC2483.
PAGE 30
LTC2483 applications information union { signed int32 bits32; struct fourbytes by; } adc_code; // // // // // adc_code.bits32 adc_code.by.te0 adc_code.by.te1 adc_code.by.te2 adc_code.by.te3 all 32 bits byte 0 byte 1 byte 2 byte 3 // Start communication with LTC2483: i2c_start(); if(i2c_write(addr | READ))// If no acknowledge, return zero { i2c_stop(); return 0; } adc_code.by.te3 = i2c_read(); adc_code.by.te2 = i2c_read(); adc_code.by.te1 = i2c_read(); adc_code.by.te0 = 0; i2c_stop(); return adc_code.
PAGE 31
LTC2483 Applications information // If read_LTC2483() does not return non-zero within this time period, something // is wrong, such as an incorrect i2c address or bus conflict. if((x = read_LTC2483(LTC248XADDR)) != 0) { // No timeout, everything is okay timeout = 0; // reset timer x ^= 0x80000000; // Invert MSB, result is 2’s complement voltage = (float) x; // convert to float voltage = voltage * 5.0 / 2147483648.
PAGE 32
LTC2483 package description DD Package DD Package 10-Lead PlasticPlastic DFN (3mm 3mm)s 3mm) 10-Lead DFN×(3mm (Reference LTC DWG # 05-08-1699 Rev C) Rev C) (Reference LTC DWG # 05-08-1699 0.70 p0.05 3.55 p0.05 1.65 p0.05 2.15 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p0.10 (4 SIDES) R = 0.125 TYP 6 0.40 p 0.10 10 1.65 p 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.
PAGE 33
LTC2483 Revision History (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 7/10 Revised Typical Application drawing 1 Added text to first paragraph of I2C Interface section 11 2483fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 34
LTC2483 Typical Application 5V C8 1µF PIC16F73 C7 0.1µF ISOTHERMAL 1.7k 1.