Datasheet
LTC2481
26
2481fc
APPLICATIONS INFORMATION
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
– V
INCM
) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (V
REFCM
– V
INCM
)/(V
REF
• R
EQ
) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 • 10
–6
• f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
Figure 21. Offset Error vs Output Data Rate and Temperature
Figure 22. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
20 40 60 80
2481 F21
10010030507090
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
CA0/f
0
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
10
50
70
2481 F22
1000
3000
40
90
100
20
30
60 80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
CA0/f
0
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
Figure 23. –FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS ERROR (ppm OF V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2481 F23
–2500
–500
40
90
100
20
30
60 80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
CA0/f
0
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
Figure 20. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for C
REF
> 1μF
V
IN
/V
REF
(V)
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2481 F20
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25°C
C
REF
= 10µF
R = 1k
R = 100
R = 500
and power supply range is typically better than 0.5%. Such
a specifi cation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by V
REF
+
and V
REF
–
, the expected drift of the dynamic current gain
error will be insignifi cant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be suffi cient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±100nA max), results in a small gain error. A 100
source resistance will create a 0.05µV typical and 5µV
maximum full-scale error.