Datasheet

LTC2482
19
2482fc
APPLICATIONS INFORMATION
A similar situation may occur during the sleep state when
CS is pulsed high-low-high in order to test the conversion
status. If the device is in the sleep state (EOC = 0), SCK
will go low. Once CS goes high (within the time period
defi ned above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a high level
before CS goes low again. This is not a concern under
normal conditions where CS remains low after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire (output only) interface.
The conversion result is shifted out of the device by an
internally generated serial clock (SCK) signal (see Figure 9).
CS may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is not externally driven low (if SCK is loaded such that the
internal pull-up cannot pull the pin high, the external SCK
mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are high (EOC = 1). Once the conversion is
complete, SCK and SDO go low (EOC = 0) indicating the
conversion has fi nished and the device has entered the low
power sleep state. The part remains in the sleep state a
minimum amount of time (1/2 the internal SCK period) then
immediately begins outputting data. The data input/output
cycle begins on the fi rst rising edge of SCK and ends after
the 24th rising edge. The output data is shifted out of the
SDO pin on each falling edge of SCK. The internally gener-
ated serial clock is output to the SCK pin. This signal may
be used to shift the conversion result into external circuitry.
EOC can be latched on the fi rst rising edge of SCK and the
last bit of the conversion result can be latched on the 24th
rising edge of SCK. After the 24th rising edge, SDO goes
high (EOC = 1) indicating a new conversion is in progress.
SCK remains high during the conversion.
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBSIG
BIT 8
TEST EOC
(OPTIONAL)
TEST EOC
BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEPSLEEP
DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z
DATA
OUTPUT
CONVERSIONCONVERSIONSLEEP
2482 F08
<t
EOCtest
TEST EOC
V
CC
f
O
V
REF
IN
+
IN
–
SCK
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
Hi-Z
Figure 8. Internal Serial Clock, Reduce Data Output Length