Datasheet

LTC2484
30
2484fd
APPLICATIONS INFORMATION
V
REF
translates into about 2.18 • 10
–6
• f
EOSC
ppm addi-
tional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the V
REF
pin when large
C
REF
values are used. The user is advised to minimize the
source impedance driving the V
REF
pin.
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be suffi cient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature
dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 0.5μV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2484 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.8sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignifi cantly short. When oper-
ated with an external conversion clock (f
O
connected to
an external oscillator), the LTC2484 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/f
EOSC
. If f
EOSC
= 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in f
EOSC
over the nominal 307.2kHz will trans-
late into a proportional increase in the maximum output
data rate. The increase in output rate is nevertheless
accompanied by three potential effects, which must be
carefully considered.
First, a change in f
EOSC
will result in a propor tional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent per-
formance degradation can be substantially reduced by
relying upon the LTC2484’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input fi lters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN
+
and IN
–
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for C
REF
> 1μF
V
IN
/V
REF
(V)
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2484 F19
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25°C
C
REF
= 10μF
R = 1k
R = 100Ω
R = 500Ω
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
– V
INCM
) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (V
REFCM
– V
INCM
)/(V
REF
• R
EQ
) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 • 10
–6
• f
EOSC
ppm.
The magnitude of the dynamic reference current depends
u p o n t h e s i z e o f t h e v e r y s t a b l e i n t e r n a l s a m p l i n g c a p a c i t o r s
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specifi cation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by V
REF
+
and GND, the expected drift of the dynamic current gain
error will be insignifi cant (about 1% of its value over the