Datasheet

LTC2484
21
2484fd
APPLICATIONS INFORMATION
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the fi rst rising edge and
the 32nd falling edge of SCK (see Figure 6). On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. If the device has
not fi nished loading the last input bit SPD of SDI by the
time CS is pulled HIGH, the SDI information is discarded
and the previous confi guration is kept. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface.
The conversion result is shifted out of the device by
an externally generated serial clock (SCK) signal (see
Figure 7). CS may be permanently tied to ground,
simplifying the user interface or transmission over an
isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is con-
cluded typically 4ms after V
CC
exceeds approximately 2V.
The level applied to SCK at this time determines if SCK
is internal or external. SCK must be driven LOW prior to
the end of POR in order to enter the external serial clock
timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the fi rst rising
edge) and the output data is shifted out of the SDO pin
on each falling edge of SCK. EOC can be latched on the
fi rst rising edge of SCK. On the 32nd falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun.
EN GS2 GS1 GS0 IM FA FB SPD
SDI*
DON’T CARE DON’T CARE
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
IM
LSB
BIT 4BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22
DATA OUTPUT CONVERSION
2484 F07
CONVERSION
V
CC
f
O
V
REF
IN
+
IN
–
SCK
SDI
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2484
3-WIRE
SPI INTERFACE
Figure 7. External Serial Clock, CS = 0 Operation