Datasheet

LTC2484
17
2484fd
APPLICATIONS INFORMATION
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifi cations but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 4 summarizes the duration of each state and the
achievable output data rate as a function of f
O
.
Ease of Use
The LTC2484 data output has no latency, fi lter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2484 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2484 automatically enters an internal reset
state when the power supply voltage V
CC
drops below
approximately 2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection.
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2484 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
Table 4. LTC2484 State Duration
STATE OPERATING MODE DURATION
CONVERT Internal Oscillator 60Hz Rejection 133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection 160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection 147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator f
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/5120 Rejection)
41036/f
EOSC
s, Output Data Rate ≤ f
EOSC
/41036 Readings/s for
1x Speed Mode
20556/
fEOSC
s, Output Data Rate ≤ f
EOSC
/20556 Readings/s for
2x Speed Mode
SLEEP As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT Internal Serial Clock f
O
= LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 0.83ms
(32 SCK Cycles)
f
O
= External Oscillator with
Frequency f
EOSC
kHz
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK Cycles)
External Serial Clock with
Frequency f
SCK
kHz
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK Cycles)
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/5120(%)
–12 –8 –4 0 4 8 12
NORMAL MODE REJECTION (dB)
2484 F03
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Figure 3. LTC2484 Nomal Mode Rejection When
Using an External Oscillator