Datasheet

LTC2484
16
2484fd
APPLICATIONS INFORMATION
indicating the initiation of a new conversion cycle. This
bit serves as EOC (bit 31) for the next conversion cycle.
Table 3 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital fi lter
(commonly implemented as a SINC or Comb fi lter). For
high resolution, low frequency applications, this fi lter is
t y p i c a l l y d e s i g n e d t o r e j e c t l i n e f r e q u e n c i e s o f 5 0 H z o r 6 0 H z
plus their harmonics. The fi lter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2484 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (f
O
)
T h e LT C 24 8 4 i n t e r n a l o s c i l l a t o r p r o v i d e s b e t t e r t h a n 110 d B
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip confi guration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2484 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the f
O
pin and turns off the internal oscillator.
The frequency f
EOSC
of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not signifi cant as long as the minimum and maximum
specifi cations for the high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2484 provides better than 110dB
normal mode rejection in a frequency range of f
EOSC
/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/5120
is shown in Figure 3.
Whenever an external clock is not present at the f
O
pin,
the converter automatically activates its internal oscilla-
tor and enters the internal conversion clock mode. The
LTC2484 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
Table 3. LTC2484 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
V
IN
*
BIT 31
EOC
BIT 30
DMY
BIT 29
SIG
BIT 28
MSB
BIT 27 BIT 26 BIT 25 … BIT 0
V
IN
* ≥ FS** 0011000…0
FS** – 1LSB 0010111…1
0.5 • FS** 0010100…0
0.5 • FS** – 1LSB 0 0 1 0 0 1 1 … 1
0 0 0 1/0*** 0 0 0 0 … 0
–1LSB 0001111…1
–0.5 • FS** 0001100…0
–0.5 • FS** – 1LSB 0 0 0 1 0 1 1 … 1
–FS** 0001000…0
V
IN
* < –FS** 0 0 0 0 1 1 1 … 1
* The differential input voltage V
IN
= IN
+
– IN
–
.
** The full-scale voltage FS = 0.5 • V
REF
.
*** The sign bit changes state during the 0 output code when the device is operating in the 2× speed mode .