LTC2484 24-Bit ∆Σ ADC with Easy Drive Input Current Cancellation FEATURES DESCRIPTION n The LTC®2484 combines a 24-bit No Latency ∆Σ™ analogto-digital converter with patented Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current.
LTC2484 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Supply Voltage (VCC) to GND ...................... –0.3V to 6V Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ –0.3V to (VCC + 0.3V) Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2484C ............................................... 0°C to 70°C LTC2484I ......................................
LTC2484 ELECTRICAL CHARACTERISTICS (2x SPEED) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) l Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) l 2 1 10 ppm of VREF ppm of VREF Offset Error 2.
LTC2484 ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2484 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode CONDITIONS (Note 15) l l l l l l l MIN 10 0.125 0.125 157.2 131.0 144.1 TYP MAX 4000 100 100 163.5 136.3 149.
LTC2484 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) –45°C 1 25°C 0 85°C –1 –2 3 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V fO = GND 2 INL (ppm OF VREF) 2 1 –45°C, 25°C, 90°C 0 –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 –0.75 VCC = 5V VREF = 5V VIN(CM) = 1.25V fO = GND 8 85°C 25°C –45°C –4 12 85°C 2 4 –45°C 0 –4 –0.75 Noise Histogram (6.8sps) NUMBER OF READINGS (%) NUMBER OF READINGS (%) –4 1.8 2484 G07 1.
LTC2484 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs Input Differential Voltage VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0.8 0.7 0.6 0.5 1.0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND TA = 25°C 0.9 RMS NOISE (μV) RMS NOISE (ppm OF VREF) 0.9 RMS Noise vs Temperature (TA) RMS Noise vs VIN(CM) 1.0 0.8 0.7 0.6 –1 0 2 1 3 5 4 RMS NOISE (μV) RMS NOISE (μV) VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C 0.9 0.8 0.7 0.6 0.5 0.5 0.4 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 1 2 3 VREF (V) –0.
LTC2484 TYPICAL PERFORMANCE CHARACTERISTICS Temperature Sensor vs Temperature 5 VCC = 5V VREF = 1.4V fO = GND 0.25 308 3 TEMPERATURE ERROR (°C) VPTAT/VREF (V) 0.30 310 VCC = 5V fO = GND 4 0.35 On-Chip Oscillator Frequency vs Temperature 2 FREQUENCY (kHz) 0.40 Temperature Sensor Error vs Temperature VREF = 1.4V 1 0 –1 –2 306 304 302 –3 –4 –30 0 30 60 TEMPERATURE (°C) 90 –5 –60 120 –30 30 60 0 TEMPERATURE (°C) On-Chip Oscillator Frequency vs VCC 306 304 302 300 2.5 3.0 3.
LTC2484 TYPICAL PERFORMANCE CHARACTERISTICS 450 400 350 300 VCC = 3V 250 1 25°C, 90°C 0 –1 200 1 90°C 0 –45°C, 25°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 0 2484 G28 NUMBER OF READINGS (%) 90°C 0 –45°C, 25°C –2 –0.25 0.25 0.75 INPUT VOLTAGE (V) RMS = 0.86μV 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V GAIN = 256 10 TA = 25°C 8 6 0.8 0.6 0.
LTC2484 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VREF (2x Speed Mode) 250 VCC = 5V VIN = 0V VIN(CM) = GND fO = GND TA = 25°C 230 OFFSET ERROR (μV) OFFSET ERROR (μV) 200 0 240 VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND TA = 25°C 150 100 PSRR vs Frequency at VCC (2x Speed Mode) 220 –40 210 200 190 2 2.5 3 4 3.5 VCC (V) 4.5 5.5 5 160 –140 1 0 2 4 3 VREF (V) 2484 G36 REJECTION (dB) –40 –60 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2484 G38 0 VCC = 4.1V DC ±1.
LTC2484 PIN FUNCTIONS SCK (Pin 9): Bidirectional Digital Clock Pin. In internal serial clock operation mode, SCK is used as the digital output for the internal serial interface clock during the data input/output period. In external serial clock operation mode, SCK is used as the digital input for the external serial interface clock during the data output period. A weak internal pull-up is automatically activated in Internal serial clock operation mode.
LTC2484 TEST CIRCUITS VCC SDO 1.69k 1.
LTC2484 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2484 is a low power, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface and automatic differential input current cancellation. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1).
LTC2484 APPLICATIONS INFORMATION Through timing control of the CS and SCK pins, the LTC2484 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.
LTC2484 APPLICATIONS INFORMATION Several applications leveraging this feature are presented in more detail in the applications section. While operating in this mode, the speed is set to normal independent of control bit SPD. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Rejection Mode (FA, FB) Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW.
LTC2484 APPLICATIONS INFORMATION indicating the initiation of a new conversion cycle. This bit serves as EOC (bit 31) for the next conversion cycle. Table 3 summarizes the output data format. As long as the voltage on the IN+ and IN– pins is maintained within the –0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 • VREF .
LTC2484 APPLICATIONS INFORMATION Ease of Use –80 NORMAL MODE REJECTION (dB) –85 The LTC2484 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. –90 –95 –100 –105 –110 –115 –120 –125 –130 –135 –140 –12 –8 –4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%) 2484 F03 Figure 3.
LTC2484 APPLICATIONS INFORMATION first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. On-Chip Temperature Sensor The LTC2484 contains an on-chip PTAT (proportional to absolute temperature) signal that can be used as a temperature sensor.
LTC2484 APPLICATIONS INFORMATION VIN = IN+ – IN–, from –FS to +FS where FS = 0.5 • VREF . Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as DC performance is maintained rail-to-rail. Input signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC.
LTC2484 APPLICATIONS INFORMATION 2.7V TO 5.5V 1μF 2 VCC 10 fO INT/EXT CLOCK LTC2484 REFERENCE VOLTAGE 0.
LTC2484 APPLICATIONS INFORMATION At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. simplifying the user interface or transmission over an isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle.
LTC2484 APPLICATIONS INFORMATION Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle (see Figure 8). In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS.
LTC2484 APPLICATIONS INFORMATION 2.7V TO 5.5V 1μF 2 VCC 10 fO INT/EXT CLOCK VCC LTC2484 REFERENCE VOLTAGE 0.
LTC2484 APPLICATIONS INFORMATION Internal Serial Clock, 3-Wire I/O, Continuous Conversion complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data input/output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge.
LTC2484 APPLICATIONS INFORMATION Preserving the Converter Accuracy The LTC2484 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the 24-bit accuracy capability of this part, some simple precautions are required. Digital Signal Levels The LTC2484’s digital interface is easy to use.
LTC2484 APPLICATIONS INFORMATION Driving the Input and Reference The input and reference pins of the LTC2484 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 11.
LTC2484 APPLICATIONS INFORMATION rithm that forces the average differential input current to zero independent of external settling errors. This allows accurate direct digitization of high impedance sensors without the need for buffers. Additional errors resulting from mismatched leakage currents must also be taken into account. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN –).
LTC2484 APPLICATIONS INFORMATION Reference Current In a similar fashion, the LTC2484 samples the differential reference pins VREF+ and GND transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations.
LTC2484 APPLICATIONS INFORMATION in 1.67 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the VREF pin and external capacitance connected to that pin are shown in Figures 15-18. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms –VIN2 /(VREF • REQ) – (0.5 • VREF • DT )/REQ in the reference pin current as expressed in Figure 11.
LTC2484 APPLICATIONS INFORMATION VREF translates into about 2.18 • 10 –6 • fEOSCppm additional INL error. Figure 19 shows the typical INL error due to the source resistance driving the VREF pin when large CREF values are used. The user is advised to minimize the source impedance driving the VREF pin. INL (ppm OF VREF) 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10μF R = 1k 2 Output Data Rate R = 100Ω When using its internal oscillator, the LTC2484 produces up to 7.
LTC2484 APPLICATIONS INFORMATION through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC.
LTC2484 APPLICATIONS INFORMATION Input Bandwidth is used with the notch set at 60Hz, the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the fO pin, the 3dB input bandwidth is 11.8 • 10 –6 • fEOSC. The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2484 input bandwidth.
LTC2484 APPLICATIONS INFORMATION at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2484 input bandwidth is shown in Figure 28. When an external oscillator of frequency fEOSC is used, the shape of the LTC2484 input bandwidth can be derived from Figure 28, 60Hz mode curve in which the horizontal axis is scaled by fEOSC/307200. The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter.
LTC2484 APPLICATIONS INFORMATION Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2484 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2484 allows external lowpass filtering without degrading the DC performance of the device.
LTC2484 0 0 –10 –10 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) APPLICATIONS INFORMATION –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 8fN 2484 F32 2484 F33 Figure 32. Input Normal Mode Rejection at DC MEASURED DATA CALCULATED DATA –20 –40 VCC = 5V VREF = 5V VIN(CM) = 2.
LTC2484 APPLICATIONS INFORMATION be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2484 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels.
LTC2484 APPLICATIONS INFORMATION Using the 2x speed mode of the LTC2484, the device bypasses the digital offset calibration operation to double the output data rate. The superior normal mode rejection is maintained as shown in Figures 30 and 31. However, the magnified details near DC and fS = 256fN are different, see Figures 39 and 40. In 2x speed mode, the bandwidth is 11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz rejection mode and 12.4Hz for the 50Hz/60Hz rejection mode.
LTC2484 APPLICATIONS INFORMATION Complete Thermocouple Measurement System with Cold Junction Compensation The LTC2484 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input has a typical offset error of 500nV (2.5μV max) offset drift of 10nV/°C and a noise level of 600nVRMS. Figure 44 (last page of this data sheet) is a complete type K thermocouple meter. The only signal conditioning is a simple surge protection network.
LTC2484 APPLICATIONS INFORMATION /*** read _ LTC2484() ************************************************************ This is the function that actually does all the work of talking to the LTC2484. The spi _ read() function performs an 8 bit bidirectional transfer on the SPI bus. Data changes state on falling clock edges and is valid on rising edges, as determined by the setup _ spi() line in the initialize() function.
LTC2484 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 p0.05 3.50 p0.05 1.65 p0.05 2.15 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 3.00 p0.10 (4 SIDES) 0.38 p 0.10 10 1.65 p 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 5) (DD10) DFN 0403 5 0.200 REF 1 0.25 p 0.05 0.50 BSC 0.75 p0.05 0.00 – 0.05 2.38 p0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1.
LTC2484 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION B 11/09 Revised Tables 2 and 3.
LTC2484 TYPICAL APPLICATION 5V PIC16F73 C8 1μF C7 0.