Datasheet

LTC2605/LTC2615/LTC2625
10
2605fa
PIN FUNCTIONS
BLOCK DIAGRAM
TIMING DIAGRAM
GND (Pin 1): Analog Ground.
V
OUT A
to V
OUT H
(Pins 2-5 and 12-15): DAC Analog Volt-
age Output. The output range is 0V to V
REF
.
REF (Pin 6): Reference Voltage Input. 0V ≤ V
REF
≤ V
CC
.
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V
CC
, GND
or leave it fl oating to select an I
2
C slave address for the
part (Table 2).
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to V
CC
.
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
is a high impedance pin while data is shifted in. It is an
open-drain N-channel output during acknowledgment. This
pin requires a pull-up resistor or current source to V
CC
.
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V
CC
, GND
or leave it fl oating to select an I
2
C slave address for the
part (Table 2).
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V
CC
, GND
or leave it fl oating to select an I
2
C slave address for the
part (Table 2).
V
CC
(Pin 16): Supply Voltage Input. 2.7V ≤ V
CC
≤ 5.5V.
2
15
1GND
V
OUT A
V
OUT B
V
OUT C
V
OUT D
REF
CA2
SCL
V
CC
V
OUT H
V
OUT G
V
OUT F
V
OUT E
CA0
CA1
SDA
2605 BD01
16
DAC A
3 14
4 13
5
7
6
8
10
11
9
12
2-WIRE INTERFACE
32-BIT SHIFT REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC H
DAC B DAC G
DAC C DAC F
DAC D DAC E
SDA
t
f
S
t
r
t
LOW
t
HD(STA)
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
t
HD(DAT)
t
SU(DAT)
t
SU(STA)
t
HD(STA)
t
SU(STO)
t
SP
t
BUF
t
r
t
f
t
HIGH
SCL
S P S
2605 F01
Figure 1