Datasheet
LTC2607/LTC2617/LTC2627
15
26071727fa
operation
Table 2
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
ADDRESS*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
1 1 1 1 All DACs
*Command and address codes not shown are reserved and should not be used.
Power-Down Mode
For power-constrained applications, the power-down mode
can be used to reduce the supply current whenever one or
both of the DAC outputs are not needed. When in power-
down, the buffer amplifiers, bias circuits and reference input
are disabled and draw essentially zero current. The DAC
outputs are put into a high impedance state, and the output
pins are passively pulled to V
REFLO
through 90k resistors.
Input-register and DAC-register contents are not disturbed
during power-down.
Either or both DAC channels can be put into power-down
mode by using command 0100b in combination with the
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2607)
Write Word Protocol for LTC2607/LTC2617/LTC1627
C2
C1
C0
A3
A2
A1
A0
D13D14D15
S
W A
SLAVE ADDRESS
1ST DATA BYTE
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
A 2ND DATA BYTE A 3RD DATA BYTE A P
2607 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2617)
C2
C1
C0
A3
A2
A1
A0
D11D12D13
D10
D9 D8 D7 D6
D5
D4
D3 D2 D1 D0 X
X
2ND DATA BYTE 3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2627)
C2
C1
C0
A3
A2
A1
A0
D9D10D11
D8
D7 D6 D5 D4
D3
D2
D1 D0 X X X
X
2ND DATA BYTE 3RD DATA BYTE
appropriate DAC address. The 16-bit data word is ignored.
The supply and reference currents are reduced by approxi-
mately 50% for each DAC powered down; the effective
resistance at REF (Pin 9) rises accordingly, becoming a
high-impedance input (typically > 1GΩ) when both DACs
are powered down.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 2 or performing an asychronous update (LDAC) as
described in the next section. The selected DAC is powered
up as its voltage output is updated. When a DAC in powered-
down state is powered up and updated, normal settling
is delayed. If one of the two DACs is in a powered- down
state prior to the update command, the power up delay is
5µs. If on the other hand, both DACs are powered down,
the main bias generation circuit has been automatically
shut down in addition to the DAC amplifiers and reference
input and so the power up delay time is
12µs (for V
CC
= 5V) or 30µs (for V
CC
= 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC registers with
the contents of the input registers. Asynchronous update
is disabled when the input word is being clocked into
the part.