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LTC2607/LTC2617/LTC2627

26071727fa

Block Diagram

Features Description

16-/14-/12-Bit Dual Rail-to-Rail

DACs with I

C Interface

The LTC

2607/LTC2617/LTC2627 are dual 16-, 14- and

12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a

12-lead DFN package. They have built-in high performance

output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply,

voltage-output DACs.

The parts use a 2-wire, I

C compatible serial interface. The

LTC2607/LTC2617/LTC2627 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). An asynchronous DAC update pin (LDAC) is

also included.

The LTC2607/LTC2617/LTC2627 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise less

than 10mV above zero scale; and after power-up, they stay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2607-1/LTC2617-1/

LTC2627-1 to mid-scale. The voltage outputs stay at mid-

scale until a valid write and update takes place.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5396245 and 6891433. Patent Pending.

applications

Smallest Pin-Compatible Dual DACs:

LTC2607: 16 Bits

LTC2617: 14 Bits

LTC2627: 12 Bits

Guaranteed Monotonic Over Temperature

27 Selectable Addresses

400kHz I

C Interface

Wide 2.7V to 5.5V Supply Range

Low Power Operation: 260µA per DAC at 3V

Power Down to 1µA, Max

High Rail-to-Rail Output Drive (±15mA, Min)

Ultralow Crosstalk (30µV)

Double-Buffered Data Latches

Asynchronous DAC Update Pin

LTC2607/LTC2617/LTC2627: Power-On Reset to

Zero Scale

LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset

to Mid-Scale

Tiny (3mm × 4mm) 12-Lead DFN Package

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

Differential Nonlinearity

(LTC2607)

811 10

5 6

21 43

2-WIRE INTERFACE

CA0 CA1 LDAC SCL SDA

REFLO GND REF V

CA2

32-BIT SHIFT REGISTER

INPUT REGISTER INPUT REGISTER

DAC REGISTER DAC REGISTER

12-/14-/16-BIT DAC

OUTB

12-/14-/16-BIT DAC

OUTA

2607 BD01a

CODE

0 16384 32768 49152 65535

DNL (LSB)

2607 BD01b

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

Summary of content (20 pages)

PAGE 1
LTC2607/LTC2617/LTC2627 16-/14-/12-Bit Dual Rail-to-Rail DACs with I2C Interface Description Features n n n n n n n n n n n n n n Smallest Pin-Compatible Dual DACs: LTC2607: 16 Bits LTC2617: 14 Bits LTC2627: 12 Bits Guaranteed Monotonic Over Temperature 27 Selectable Addresses 400kHz I2C Interface Wide 2.7V to 5.
PAGE 2
LTC2607/LTC2617/LTC2627 Absolute Maximum Ratings Pin Configuration (Note 1) Any Pin to GND............................................. –0.3V to 6V Any Pin to VCC.............................................. –6V to 0.3V Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 125°C Lead Temperature (Soldering, 10 sec)................... 300°C Operating Temperature Range: LTC2607C/LTC2617C/LTC2627C LTC2607C-1/LTC2617C-1/LTC2627C-1.....
PAGE 3
LTC2607/LTC2617/LTC2627 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted.
PAGE 4
LTC2607/LTC2617/LTC2627 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted.
PAGE 5
LTC2607/LTC2617/LTC2627 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1 MIN MIN MIN CONDITIONS TYP MAX TYP MAX TYP MAX UNITS AC Performance tS Settling Time (Note 7) ±0.024% (±1LSB at 12 Bits) ±0.
PAGE 6
LTC2607/LTC2617/LTC2627 Typical Performance Characteristics LTC2607 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 16 0.4 –8 0.2 INL (LSB) DNL (LSB) 0 0 –0.2 –0.4 –16 16384 32768 CODE 49152 –1.0 65535 0 16384 32768 CODE 49152 2607 G01 –10 10 30 50 TEMPERATURE (°C) 70 90 DNL vs VREF 1.5 VCC = 5.5V 24 0.6 VCC = 5.5V 1.0 16 0.4 DNL (POS) 0.2 INL (LSB) DNL (LSB) –30 2607 G03 INL vs VREF 32 VCC = 5V VREF = 4.096V 0 –0.
PAGE 7
LTC2607/LTC2617/LTC2627 Typical Performance Characteristics LTC2617 Integral Nonlinearity (INL) 8 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 6 0.6 DNL (LSB) INL (LSB) 0.4 2 0 –2 0 SCL 2V/DIV –0.2 –0.6 –6 0 4096 8192 CODE 12288 –1.0 16383 0 4096 8192 CODE 12288 2607 G09 2607 G11 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 16383 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 1.5 8.
PAGE 8
LTC2607/LTC2617/LTC2627 Typical Performance Characteristics LTC2607/LTC2617/LTC2627 Current Limiting CODE = MID-SCALE 0.06 0.2 ∆VOUT (mV) 0 VREF = VCC = 3V –0.04 0 –0.2 VREF = VCC = 3V –0.6 –0.08 20 30 –1.0 –35 40 –15 –5 5 IOUT (mA) 15 25 GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 90 2 0.2 0.1 0 –0.1 –0.2 1 0 –1 –2 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 –3 2.5 90 3 3.5 2607 G19 4 VCC (V) 4.5 5 5.5 2607 G20 ICC Shutdown vs VCC 450 0.3 400 0.2 350 0.
PAGE 9
LTC2607/LTC2617/LTC2627 Typical Performance Characteristics LTC2607/LTC2617/LTC2627 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset to Zeroscale TRANSITION FROM MS-1 TO MS VOUT 10mV/DIV VOUT 0.5V/DIV 9TH CLOCK OF 3RD DATA BYTE SCL 2V/DIV VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5µs/DIV TRANSITION FROM MS TO MS-1 2.5µs/DIV 2607 G23 Headroom at Rails vs Output Current 4mV PEAK VOUT 10mV/DIV 2607 G24 Supply Current vs Logic Voltage 950 VREF = VCC 5V SOURCING 850 2.5 1V/DIV 2.
PAGE 10
LTC2607/LTC2617/LTC2627 Typical Performance Characteristics LTC2607/LTC2617/LTC2627 50 Short-Circuit Output Current vs VOUT (Sinking) 40 30 20 10 0 VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V –10 10mA/DIV 10mA/DIV 0 VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC Short-Circuit Output Current vs VOUT (Sourcing) –20 –30 –40 0 1 2 3 1V/DIV 4 5 6 –50 0 1 2 3 1V/DIV 2607 G32 4 5 6 2607 G33 Pin Functions CA0 (Pin 1): Chip Address Bit 0.
PAGE 11
LTC2607/LTC2617/LTC2627 Block Diagram REFLO 11 GND 10 REF 9 VCC 12-/14-/16-BIT DAC 12 VOUTA 8 12-/14-/16-BIT DAC DAC REGISTER DAC REGISTER INPUT REGISTER INPUT REGISTER VOUTB 7 32-BIT SHIFT REGISTER 2-WIRE INTERFACE CA0 1 CA1 2 LDAC 3 SCL 4 SDA CA2 5 6 2607 BD Test Circuits Test Circuit 1 Test Circuit 2 VDD 100Ω CAn RINH/RINL/RINF CAn VIH(CAn)/VIL(CAn) GND 2607 TC 26071727fa 11
PAGE 12
2 1 SCL 3 SA4 4 SA3 5 SA2 SLAVE ADDRESS 6 SA1 7 SA0 8 S tHD(STA) tLOW tr tHD(DAT) tHIGH tSU(DAT) tf tSU(STA) 9 1 C3 2 C2 3 C1 4 C0 5 A3 1ST DATA BYTE 6 A2 LDAC SCL 7 A1 8 A0 2 S Figure 2b t1 Figure 2a 1 9TH CLOCK OF 3RD DATA BYTE 9 ACK Figure 1 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS ACK tf 3 4 2607 F02b 5 2ND DATA BYTE tHD(STA) 6 7 8 tSU(STO) tSP 9 ACK tr P 1 tBUF 2 S 3 4 5 3RD DATA BYTE 2607 F01 6 7 8 9 ACK t1
PAGE 13
LTC2607/LTC2617/LTC2627 Operation Power-On Reset The LTC2607/LTC2617/LTC2627 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. The LTC2607-1/ LTC2617‑1/LTC2627-1 set the voltage outputs to midscale when power is first applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time.
PAGE 14
LTC2607/LTC2617/LTC2627 Operation in 27 selectable addresses for the part. The slave address assignments are shown in Table 1. Table 1.
PAGE 15
LTC2607/LTC2617/LTC2627 Operation Write Word Protocol for LTC2607/LTC2617/LTC1627 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE C2 C1 C0 A3 A2 3RD DATA BYTE A P INPUT WORD Input Word (LTC2607) C3 A A1 A0 D15 D14 D13 D12 D11 D10 D9 1ST DATA BYTE 2ND DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 D0 3RD DATA BYTE Input Word (LTC2617) C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 1ST DATA BYTE D8 D7 2ND DATA BYTE D6 D5 D4 D3 D2 D1 D0 X X X X 3RD DATA BYTE Input Word (LTC2627)
PAGE 16
LTC2607/LTC2617/LTC2627 Operation If a complete input word has been written to the part, a low on the LDAC pin causes the DAC registers to be updated with the contents of the input registers. If the input word is being written to the part, a low going pulse on the LDAC pin before the completion of three bytes of data powers up the DACs but does not cause the outputs to be updated.
PAGE 17
X = DON’T CARE 3 4 SA3 0V OUTPUT VOLTAGE SA4 SA3 5 6 SA1 SA1 7 SA0 SA0 1 C3 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 A3 A3 COMMAND 6 A2 A2 7 A1 A1 8 A0 A0 9 ACK 1 D15 2 D14 3 D13 4 5 D11 MS DATA D12 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 3 D5 (b) OUTPUT VOLTAGE 0 (a) 32, 768 INPUT CODE VREF = VCC 65, 535 INPUT CODE (c) 4 5 D3 LS DATA D4 VREF = VCC Figure 4.
PAGE 18
LTC2607/LTC2617/LTC2627 Package Description DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695 Rev D) 0.70 p0.05 3.60 p0.05 2.20 p0.05 3.30 p0.05 1.70 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p0.10 (2 SIDES) 7 R = 0.115 TYP 0.40 p 0.10 12 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) 0.200 REF 3.30 p0.10 3.00 p0.10 (2 SIDES) 1.70 p 0.10 0.75 p0.05 6 0.25 p 0.
PAGE 19
LTC2607/LTC2617/LTC2627 Revision History REV DATE DESCRIPTION A 1/10 Revised Features PAGE NUMBER 1 Added Pin Configuration and Updated Order Information 2 Added Text to Serial Digital Interface Section 13 26071727fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 20
LTC2607/LTC2617/LTC2627 Typical Application Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters 5V 5V VREF 1V TO 5V 3 LDAC 1 CA0 2 CA1 6 CA2 I2C BUS 8 6 VCC REF VOUTB LTC2607 7 100Ω 7.5k 0.1µF 2 FSSET 3 CH 1 DAC OUTPUT B 4 100Ω 12 VOUTA 5 SCL SDA DAC GND REFLO OUTPUT A 10, 13 1 VCC 9 SCK 8 SDO 7 CS LTC2422 7.