Datasheet

LTC2205-14
22
220514fb
Internal Dither
The LTC2205-14 is a 14-bit ADC with a very linear
transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
As shown in Figure 14, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The
dither DAC is calibrated to result in less than 0.5dB
elevation in the noise fl oor of the ADC, as compared to
the noise fl oor with dither off.
APPLICATIONS INFORMATION
Figure 13. Descrambling a Scrambled Digital Output
Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit
+–
AIN
–
AIN
+
S/H
AMP
DIGITAL
SUMMATION
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
14-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
CLKOUT
OF
D13
•
•
•
D0
ENC
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
DITH
ENC
ANALOG
INPUT
220514 F14
LTC2205-14
•
•
•
D1
D0
D2
D12
D13
LTC2205-14
PC BOARD
FPGA
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
22054 F13