Datasheet

LTC2205-14
13
220514fb
Figure 1. Functional Block Diagram
BLOCK DIAGRAM
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC
+
ENC
–
CORRECTION LOGIC
AND
SHIFT REGISTER
DITHM0DE
OGND
CLKOUT+
CLKOUT–
OF
D13
D12
OV
DD
D1
D0
220514 F01
INPUT
S/H
A
IN
–
A
IN
+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
PGA RAND
OESHDN
•
•
•
V
DD
GND
PGA
SENSE
V
CM
BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
TIMING DIAGRAM
t
H
t
D
t
C
t
L
N – 7 N – 6 N – 5 N – 4 N – 3
ANALOG
INPUT
ENC
–
ENC
+
CLKOUT
–
CLKOUT
+
D0-D13, OF
220514 TD01
t
AP
N + 1
N + 2
N + 4
N + 3
N