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LTC2205-14

220514fb

14-Bit, 65Msps ADC

The LTC

2205-14 is a sampling 14-bit A/D converter

designed for digitizing high frequency, wide dynamic range

signals up to input frequencies of 700MHz. The input range

of the ADC can be optimized with the PGA front end.

The LTC2205-14 is perfect for demanding communications

applications, with AC performance that includes 78.3dB

SNR and 98dB spurious free dynamic range (SFDR).

Ultralow jitter of 90fs

RMS

allows undersampling of high

input frequencies with excellent noise performance.

Maximum DC specs include ±1.5LSB INL, ±1LSB DNL

(no missing codes).

A separate output power supply allows the CMOS output

swing to range from 0.5V to 3.6V.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer

allows high performance at full speed with a wide range

of clock duty cycles.

Telecommunications

Receivers

Cellular Base Stations

Spectrum Analysis

Imaging Systems

ATE

Sample Rate: 65Msps

78.3dB SNR and 98dB SFDR (2.25V

P-P

Range)

SFDR >90dB at 140MHz (1.5V

P-P

Input Range)

PGA Front End (2.25V

P-P

or 1.5V

P-P

Input Range)

700MHz Full Power Bandwidth S/H

Optional Internal Dither

Optional Data Output Randomizer

Single 3.3V Supply

Power Dissipation: 600mW

Optional Clock Duty Cycle Stabilizer

Out-of-Range Indicator

Pin Compatible Family

105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)

80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)

65Msps: LTC2205 (16-Bit)

40Msps: LTC2204 (16-Bit)

48-Pin (7mm × 7mm) QFN Package

LTC2205-14: 32K Point FFT,

= 5.1MHz, –1dBFS,

PGA = 0, DITH = 0

–

S/H

AMP

CORRECTION

LOGIC AND

SHIFT REGISTER

OUTPUT

DRIVERS

14-BIT

PIPELINED

ADC CORE

INTERNAL ADC

REFERENCE

GENERATOR

1.25V

COMMON MODE

BIAS VOLTAGE

CLOCK/DUTY

CYCLE

CONTROL

D13

•

ENC PGA SHDN DITH MODE OE RANDENC

ANALOG

INPUT

220514 TA01

0.5V TO 3.6V

3.3V

SENSE

OGND

2.2μF

0.1μF

GND

ADC CONTROL INPUTS

AIN

–

CLKOUT

0.1μF

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the

ert

of their res

ective owners.

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–80

–20

–10

10 20 25

220514 G04

–100

–110

–120

–40

–60

–90

–30

–130

–50

–70

515 30

FEATURES

DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION

Summary of content (28 pages)

PAGE 1
LTC2205-14 14-Bit, 65Msps ADC FEATURES DESCRIPTION n The LTC®2205-14 is a sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end. n n n n n n n n n n n n Sample Rate: 65Msps 78.3dB SNR and 98dB SFDR (2.25VP-P Range) SFDR >90dB at 140MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.
PAGE 2
LTC2205-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION OVDD = VDD (Notes 1 and 2) Supply Voltage (VDD) .................................. –0.3V to 4V Digital Output Ground Voltage (OGND)....... –0.3V to 1V Analog Input Voltage (Note 3) .....–0.3V to (VDD + 0.3V) Digital Input Voltage ....................–0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation............................................2000mW Operating Temperature Range LTC2205-14C .............
PAGE 3
LTC2205-14 ANALOG INPUT The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN–) MIN 3.135V ≤ VDD ≤ 3.465V l TYP MAX UNITS 1.5 to 2.25 VP-P VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1 1.
PAGE 4
LTC2205-14 DYNAMIC ACCURACY The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS SFDR 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) Spurious Free Dynamic Range 4th Harmonic or Higher dBc dBc 98 98 dBc dBc 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 95 95 dBc dBc 170MHz Input (2.
PAGE 5
LTC2205-14 COMMON MODE BIAS CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.15 1.25 1.35 VCM Output Tempco IOUT = 0 VCM Line Regulation VCM Output Resistance UNITS V ±40 ppm/°C 3.135V ≤ VDD ≤ 3.
PAGE 6
LTC2205-14 TIMING CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX fS Sampling Frequency l 1 tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l tH ENC High Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l tAP Sample-and-Hold Aperture Delay 65 MHz 6.40 4.60 7.69 7.
PAGE 7
LTC2205-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205-14: INL (Integral Nonlinearity) vs Code LTC2205-14: DNL (Differential Nonlinearity) vs Code 1.5 LTC2205-14: Grounded Input Histogram 250,000 1.00 0.75 1.0 200,000 0.50 0.25 0 150,000 COUNT DNL (LSB) INL (LSB) 0.5 0 100,000 –0.25 –0.5 –0.50 –1.0 50,000 –0.75 –1.5 0 4096 8192 CODE 12288 16384 –1.
PAGE 8
LTC2205-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205-14: 32K Point FFT, –1dBFS, fIN = 15.1MHz, PGA = 0, DITH = 0 LTC2205-14: 32K Point FFT, –25dBFS, fIN = 15.1MHz, PGA = 0, DITH = 0 LTC2205-14: 32K Point FFT, –1dBFS, fIN = 15.
PAGE 9
LTC2205-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205-14: 32K Point FFT, –40dBFS, fIN = 70.1MHz, PGA = 0, DITH = 0 LTC2205-14: 32K Point FFT, –1dBFS, fIN = 140.1MHz, PGA = 0, DITH = 0 LTC2205-14: 32K Point FFT, –40dBFS, fIN = 70.
PAGE 10
LTC2205-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205-14: 32K Point FFT, fIN1 = 64.1MHz, –7dBFS, fIN2 = 70.1MHz, –7dBFS, PGA = 0, DITH = 0 120 120 110 110 100 100 90 80 70 60 50 40 0 5 10 20 25 15 FREQUENCY (MHz) 30 70 60 50 40 30 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 220514 G30 LTC2205-14: SFDR vs Input Level, fIN = 14.9MHz, RAND = 1, DITH = 0 LTC2205-14: SFDR vs Input Level, fIN = 70.
PAGE 11
LTC2205-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205-14: SFDR vs Input Frequency, RAND = 1, DITH = 1 LTC2205-14: SFDR and SNR vs Sample Rate, fIN = 5.1MHz, RAND = 0, DITH = 0 LTC2205-14: SNR vs Input Frequency, RAND = 1, DITH = 0 110 110 79 SFDR (dBc) AND SNR (dBFS) 78 77 PGA = 1 SNR (dBFS) SFDR (dBc) 100 90 PGA = 0 PGA = 0 76 75 PGA = 1 80 SFDR 100 90 80 74 0 73 50 150 200 100 INPUT FREQUENCY (MHz) 250 0 50 220414 G38 220514 G40 220 110 0.05 210 0 VDD = 3.
PAGE 12
LTC2205-14 PIN FUNCTIONS SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended. VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
PAGE 13
LTC2205-14 BLOCK DIAGRAM AIN+ AIN– VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER ADC CLOCKS RANGE SELECT OVDD SENSE ADC REFERENCE PGA VCM BUFFER CLKOUT+ CLKOUT– OF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • VOLTAGE REFERENCE OGND ENC+ ENC– SHDN PGA RAND M0DE OE D13 D12 D1 D0 220514 F01
PAGE 14
LTC2205-14 OPERATION DYNAMIC PERFORMANCE by the presence of another sinusoidal input at a different frequency. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 15
LTC2205-14 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2205-14 is a CMOS pipelined multi-step converter with a front-end PGA. As shown in Figure 1, the converter has ﬁve pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range.
PAGE 16
LTC2205-14 APPLICATIONS INFORMATION During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time.
PAGE 17
LTC2205-14 APPLICATIONS INFORMATION Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than ﬂux coupled center tap transformers.
PAGE 18
LTC2205-14 APPLICATIONS INFORMATION VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT + CM – LTC2205-14 AIN+ 25Ω LTC2205-14 12pF + – RANGE SELECT AND GAIN CONTROL 2.2μF AIN– 25Ω AMPLIFIER = LTC6600-20, LTC1993, ETC. 12pF TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE INTERNAL ADC REFERENCE SENSE PGA 2.5V BANDGAP REFERENCE 220514 F05 VCM Figure 5. DC Coupled Input with Differential Ampliﬁer BUFFER 1.25V 2.
PAGE 19
LTC2205-14 APPLICATIONS INFORMATION PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be worse by up to approximately 2dB.
PAGE 20
LTC2205-14 APPLICATIONS INFORMATION ENC+ VTHRESHOLD = 1.6V 1.6V ENC– LTC2205-14 0.1μF 220514 F09 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter DIGITAL OUTPUTS 3.3V MC100LVELT22 Digital Output Buffers 3.3V 130Ω Q0 130Ω ENC+ D0 ENC– LTC2205-14 Q0 83Ω The lower limit of the LTC2205-14 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors.
PAGE 21
LTC2205-14 APPLICATIONS INFORMATION Data Format LTC2205-14 The LTC2205-14 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD . An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin. CLKOUT OF OF D13 D13/D0 D12 Table 1.
PAGE 22
LTC2205-14 APPLICATIONS INFORMATION Internal Dither PC BOARD FPGA The LTC2205-14 is a 14-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.
PAGE 23
LTC2205-14 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2205-14 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2205-14 has been optimized for a ﬂowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible.
PAGE 24
LTC2205-14 APPLICATIONS INFORMATION Ordering Guide: DEMO BOARD NUMBER PART NUMBER RESOLUTION SPEED INPUT FREQUENCY USB I/F BOARD DC918A-A LTC2207CUK 16-Bit 105Msps 1MHz to 70MHz DC718 DC918A-B LTC2207CUK 16-Bit 105Msps 70MHz to 140MHz DC718 DC918A-C LTC2206CUK 16-Bit 80Msps 1MHz to 70MHz DC718 DC918A-D LTC2206CUK 16-Bit 80Msps 70MHz to 140MHz DC718 DC918A-E LTC2205CUK 16-Bit 65Msps 1MHz to 70MHz DC718 DC918A-F LTC2205CUK 16-Bit 65Msps 70MHz to 140MHz DC718 DC918A-G
PAGE 25
LTC2205-14 APPLICATIONS INFORMATION Silkscreen Top Top Side Inner Layer 2 Inner Layer 3 220514fb 25
PAGE 26
LTC2205-14 APPLICATIONS INFORMATION Inner Layer 4 Inner Layer 5 Bottom Side Silkscreen Bottom 220514fb 26
PAGE 27
LTC2205-14 PACKAGE DESCRIPTION UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ±0.05 5.15 ± 0.05 5.50 REF 6.10 ±0.05 7.50 ±0.05 (4 SIDES) 5.15 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 CHAMFER C = 0.35 5.15 ± 0.10 5.50 REF (4-SIDES) 5.15 ± 0.
PAGE 28
LTC2205-14 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Ampliﬁer/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.