Datasheet

LTC4267
27
4267fc
with minimum trace lengths and minimum capacitance.
In a nonisolated application, R1, and R2 should be placed
as close as possible to the V
FB
pin of the LTC4267 and
C
C
should be placed close to the I
TH
/RUN pin of the
LTC4267.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267 in a PD.
The PD interface section of the LTC4267 is relatively im-
mune to layout problems. Excessive parasitic capacitance
on the R
CLASS
pin should be avoided. If using the DHC
package, include an electrically isolated heat sink to which
the exposed pad on the bottom of the package can be
soldered. For optimum thermal performance, make the
heat sink as large as possible. The SIGDISA pin is adjacent
to the V
PORTP
pin and any coupling, whether resistive
APPLICATIO S I FOR ATIO
WUUU
or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left fl oating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
Electro Static Discharge and Surge Protection
The LTC4267 is specifi ed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
PORTN
and V
PORTP
) can
routinely see peak voltages in excess of 10kV. To protect
the LTC4267, it is highly recommended that a transient
voltage suppressor be installed between the diode bridge
and the LTC4267 (D3 in Figure 2).