Datasheet

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LTC2444/LTC2445/

LTC2448/LTC2449

2444589fb

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

■

High Speed Multiplexing

■

Weight Scales

■

Auto Ranging 6-Digit DVMs

■

Direct Temperature Measurement

■

High Speed Data Acquisition

■

Up to 8 Differential or 16 Single-Ended Input

Channels

■

Up to 8kHz Output Rate

■

Up to 4kHz Multiplexing Rate

■

Selectable Speed/Resolution

■

2µV

RMS

Noise at 1.76kHz Output Rate

■

200nV

RMS

Noise at 13.8Hz Output Rate with

Simultaneous 50/60Hz Rejection

■

Guaranteed Modulator Stability and Lock-Up

Immunity for any Input and Reference Conditions

■

0.0005% INL, No Missing Codes

■

Autosleep Enables 20µA Operation at 6.9Hz

■

<5µV Offset (4.5V < V

< 5.5V, – 40°C to 85°C)

■

Differential Input and Differential Reference with

GND to V

Common Mode Range

■

No Latency Mode, Each Conversion is Accurate Even

After a New Channel is Selected

■

Internal Oscillator—No External Components

■

LTC2445/LTC2449 Include MUXOUT/ADCIN for

External Buffering or Gain

■

Tiny QFN 5mm x 7mm Package

24-Bit High Speed

8-/16-Channel ∆Σ ADCs with

Selectable Speed/Resolution

The LTC

2444/LTC2445/LTC2448/LTC2449 are 8-/16-

channel (4-/8-differential) high speed 24-bit No Latency

∆Σ

ADCs. They use a proprietary delta-sigma architec-

ture enabling variable speed/resolution. Through a simple

4-wire serial interface, ten speed/resolution combinations

6.9Hz/280nV

RMS

to 3.5kHz/25µV

RMS

(4kHz with external

oscillator) can be selected with no latency between con-

version results or shift in DC accuracy (offset, full-scale,

linearity, drift). Additionally, a 2X speed mode can be

selected enabling output rates up to 7kHz (8kHz if an

external oscillator is used) with one cycle latency.

Any combination of single-ended or differential inputs can

be selected with a common mode input range from ground

to V

, independent of V

REF

. While operating in the 1X

speed mode the first conversion following a new speed,

resolution, or channel selection is valid. Since there is no

settling time between conversions, all 8 differential chan-

nels can be scanned at a rate of 500Hz. At the conclusion

of each conversion, the converter is internally reset elimi-

nating any memory effects between successive conver-

sions and assuring stability of the high order delta-sigma

modulator.

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTC2444/LTC2448

Speed vs RMS Noise

Simple 24-Bit Variable Speed Data Acquisition System

SDI

SCK

SDO

REF

4.5V TO 5.5V

1µF

COM

REF

–

GND

THERMOCOUPLE

VARIABLE SPEED/

RESOLUTION

DIFFERENTIAL

24-BIT ∆Σ ADC

16-CHANNEL

MUX

–

2444 TA01

4-WIRE

SPI INTERFACE

LTC2448

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

(SIMULTANEOUS 50Hz/60Hz

REJECTION AT 6.9Hz OUTPUT RATE)

CH0

CH1

•

CH7

CH8

CH15

CONVERSION RATE (Hz)

0.1

RMS NOISE (µV)

100

10 100

2440 TA02

1000 10000

2.8µV AT 880Hz

280nV AT 6.9Hz

(50/60Hz REJECTION)

= 5V

REF

= 5V

= V

–

= 0V

2X SPEED MODE

NO LATENCY MODE

No Latency ∆Σ is a trademark of Linear Technology Corporation.

Summary of content (28 pages)

PAGE 1
LTC2444/LTC2445/ LTC2448/LTC2449 24-Bit High Speed 8-/16-Channel ∆Σ ADCs with Selectable Speed/Resolution DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Up to 8 Differential or 16 Single-Ended Input Channels Up to 8kHz Output Rate Up to 4kHz Multiplexing Rate Selectable Speed/Resolution 2µVRMS Noise at 1.76kHz Output Rate 200nVRMS Noise at 13.8Hz Output Rate with Simultaneous 50/60Hz Rejection Guaranteed Modulator Stability and Lock-Up Immunity for any Input and Reference Conditions 0.
PAGE 2
LTC2444/LTC2445/ LTC2448/LTC2449 U W W W ABSOLUTE AXI U RATI GS (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 6V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.
PAGE 3
LTC2444/LTC2445/ LTC2448/LTC2449 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) ● Integral Nonlinearity VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF– = GND, VINCM = 1.
PAGE 4
LTC2444/LTC2445/ LTC2448/LTC2449 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 4.5V ≤ VCC ≤ 5.5V (Note 8) ● VIL Low Level Input Voltage SCK 4.5V ≤ VCC ≤ 5.
PAGE 5
LTC2444/LTC2445/ LTC2448/LTC2449 UW TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 6
LTC2444/LTC2445/ LTC2448/LTC2449 U U U PI FU CTIO S GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH15 (Pins 8-23): LTC2448/LTC2449 Analog Inputs. May be programmed for single-ended or differential mode. CH0 to CH7 (Pins 9, 10, 13, 14, 17, 18, 21, 22): LTC2444/ LTC2445 Analog Inputs.
PAGE 7
LTC2444/LTC2445/ LTC2448/LTC2449 W FU CTIO AL BLOCK DIAGRA U INTERNAL OSCILLATOR U VCC GND FO (INT/EXT) AUTOCALIBRATION AND CONTROL REF + REF – CH0 CH1 IN + • • • CH15 COM MUX IN – – + DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR SDI SCK SDO CS SERIAL INTERFACE DECIMATING FIR ADDRESS 2444 F01 Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO SDO Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2440 TA03 W Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD = 20pF CLOAD = 20pF 2440 TA04 U 1.
PAGE 8
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Initially, the LTC2444/LTC2445/LTC2448/LTC2449 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10µA. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
PAGE 9
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO LTC2448/LTC2449 convert the bipolar differential input signal, VIN = IN+ – IN– (where IN+ and IN– are the selected input channels), from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. MUXOUT/ADCIN There are two differences between the LTC2444/LTC2448 and the LTC2445/LTC2449.
PAGE 10
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SCK SDI 1 0 EN SGL ODD A2 A1 A0 OSR3 OSR2 OSR1 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 OSR0 TWOX BIT 20 BIT 19 BIT 0 Hi-Z SDO EOC “0” SIG Hi-Z LSB MSB BUSY 2444 F04 Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing first falling edge of SCK.
PAGE 11
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO external SCK mode is selected by tying EXT (Pin 3) LOW for external SCK and HIGH for internal SCK. Serial Data Output (SDO) The serial data output pin, SDO (Pin 37), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states.
PAGE 12
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO Table 3.
PAGE 13
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Table 4.
PAGE 14
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Table 5. LTC2444/LTC2445/LTC2448/LTC2449 Speed/Resolution Selection OSR3 OSR2 OSR1 OSR0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 CONVERSION RATE RMS RMS TWOX INTERNAL EXTERNAL NOISE NOISE ENOB ENOB 9MHz 10.
PAGE 15
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Speed Multiplier Mode In addition to selecting the speed/resolution, a speed multiplier mode is used to double the output rate while maintaining the selected resolution. The last bit of the 5-bit speed/resolution control word (TWOX, see Table 5) determines if the output rate is 1X (no speed increase) or 2X (double the selected speed).
PAGE 16
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 4. The serial clock mode is selected by the EXT pin. To select the external serial clock mode, EXT must be tied low.
PAGE 17
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO As described above, CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin. sequence is aborted prior to the 13th rising edge of SCK, the new input data is ignored, and the previously selected speed/resolution and channel are used for the next conversion cycle.
PAGE 18
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO External Serial Clock, 2-Wire I/O indicating the conversion result is ready. EOC = 1 (BUSY = 1) while the conversion is in progress and EOC = 0 (BUSY = 0) once the conversion enters the low power sleep state. On the falling edge of EOC/BUSY, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK.
PAGE 19
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Internal Serial Clock, Single Cycle Operation sion and goes LOW at the conclusion. It remains LOW until the result is read from the device. This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 7.
PAGE 20
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin.
PAGE 21
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO Internal Serial Clock, 2-Wire I/O, Continuous Conversion device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (≈500ns) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin.
PAGE 22
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2444/LTC2445/ LTC2448/LTC2449 significantly simplify antialiasing filter requirements. The LTC2444/LTC2445/LTC2448/LTC2449’s speed/resolution is determined by the over sample ratio (OSR) of the on-chip digital filter. The OSR ranges from 64 for 3.
PAGE 23
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO If FO is grounded, fS is set by the on-chip oscillator at 1.8MHz ±5% (over supply and temperature variations). At an OSR of 32,768, the first NULL is at fN = 55Hz and the no latency output rate is fN/8 = 6.9Hz. At the maximum OSR, the noise performance of the device is 280nVRMS (LTC2444/ LTC2448) and 200nVRMS (LTC2445/LTC2449) with better than 80dB rejection of 50Hz ±2% and 60Hz ±2%.
PAGE 24
LTC2444/LTC2445/ LTC2448/LTC2449 U U W U APPLICATIO S I FOR ATIO Reduced Power Operation Average Input Current In addition to adjusting the speed/resolution of the LTC2444/LTC2445/LTC2448/LTC2449, the speed/resolution/power dissipation may also be adjusted using the automatic sleep mode. During the conversion cycle, the LTC2444/LTC2445/LTC2448/LTC2449 draw 8mA supply current independent of the programmed speed.
PAGE 25
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Input Bandwidth and Frequency Rejection First Notch Frequency The combined effect of the internal SINC4 digital filter and the digital and analog autocalibration circuits determines the LTC2444/LTC2445/LTC2448/LTC2449 input bandwidth and rejection characteristics. The digital filter’s response can be adjusted by setting the oversample ratio (OSR) through the SPI interface or by supplying an external conversion clock to the fo pin.
PAGE 26
LTC2444/LTC2445/ LTC2448/LTC2449 U W U U APPLICATIO S I FOR ATIO Example: If an amplifier (e.g. LT1219) driving the input of an LTC2444/LTC2445/LTC2448/LTC2449 has wideband noise of 33nV/√Hz, band-limited to 1.8MHz, the total noise entering the ADC input is: Automatic Offset Calibration of External Buffers/Amplifiers 33nV/√Hz • √1.8MHz = 44.3µV. When the ADC digitizes the input, its digital filter filters out the wideband noise from the input signal.
PAGE 27
LTC2444/LTC2445/ LTC2448/LTC2449 U PACKAGE DESCRIPTIO UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.20 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.20 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (2 SIDES) 3.15 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 0.435 0.18 0.18 37 38 PIN 1 TOP MARK (SEE NOTE 6) 1 0.23 2 5.15 ± 0.10 (2 SIDES) 7.
PAGE 28
LTC2444/LTC2445/ LTC2448/LTC2449 U TYPICAL APPLICATIO External Buffers Provide High Impedance Inputs and Amplifier Offsets are Cancelled SDI LTC2449 HIGH SPEED ∆Σ ADC ADCINP 2 SCK SDO CS – 1/2 LT1368 3 ADCINN MUX MUXOUTP CH0-CH15/ COM MUXOUTN 17 + 1 0.1µF (EXTERNAL AMPLIFIERS) 6 – 5V 8 1/2 LT1368 5 + 7 4 0.1µF 2444589 TA05 0V RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.