Datasheet

LTM4600HV
9
4600hvfc
APPLICATIO S I FOR ATIO
WUU
U
voltage is margined up. The output voltage is margined
down when Q
DOWN
is on and Q
UP
is off. If the output
voltage V
O
needs to be margined up/down by ±M%, the
resistor values of R
UP
and R
DOWN
can be calculated from
the following equations:
()••(%)
()
.
RR V M
RR k
V
SET UP O
SET UP
1
100
06
+
+Ω
=
RV M
RkR
V
SET O
SET DOWN
••(–%)
()
.
1
100
06
+Ω
=
Input Capacitors
The LTM4600HV μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 21, the bulk input capacitor C
IN
is selected
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
D
V
V
O
IN
=
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
I
I
DD
CIN RMS
OMAX
()
()
%
••( )=−
η
1
In the above equation, η% is the estimated effi ciency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements over temperature.
In Figure 21, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R (for extended temperature range), 10μF ceramic
capacitors are recommended. This decoupling capacitor
The typical LTM4600HV application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4600HV has an internal
0.6V±1% reference voltage. As shown in the block diagram,
a 100k/0.5% internal feedback resistor connects V
OUT
and V
OSET
pins. Adding a resistor R
SET
from V
OSET
pin to
SGND pin programs the output voltage:
VV
kR
R
O
SET
SET
=
+
06
100
.•
Table 1 shows the standard values of 1% R
SET
resistor
for typical output voltages:
Table 1.
R
SET
(kΩ)
Open 100 66.5 49.9 43.2 31.6 22.1 13.7
V
O
(V)
0.6 1.2 1.5 1.8 2 2.5 3.3 5
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600HV. In addition to the feedback
resistor R
SET
, several external components are added.
Turn off both transistor Q
UP
and Q
DOWN
to disable the
margining. When Q
UP
is on and Q
DOWN
is off, the output
Figure 2. LTM4600HV Margining Implementation
PGND SGND
4600hv F02
LTM4600HV
V
OUT
V
OSET
R
SET
R
UP
Q
UP
100k
2N7002
R
DOWN
Q
DOWN
2N7002