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LTC2606/LTC2616/LTC2626

26061626fb

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

16-/14-/12-Bit Rail-to-Rail DACs

with I

C Interface

The LTC

2606/LTC2616/LTC2626 are single 16-, 14- and

12-bit,

2.7V-to-5.5V rail-to-rail voltage output DACs in a

10-lead DFN package. They have built-in high performance

output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply, volt-

age-output DACs.

The parts use a 2-wire, I

C compatible serial interface. The

LTC2606/LTC2616/LTC2626 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). An asynchronous DAC update pin (LDAC) is

also included.

The LTC2606/LTC2616/LTC2626 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise less

than 10mV above zero scale; and after power-up, they stay

at zero scale until a valid write and update take place. The

power-on reset circuit resets the LTC2606-1/LTC2616-1/

LTC2626-1 to mid-scale. The voltage outputs stay at mid-

scale until a valid write and update take place.

Differential Nonlinearity

(LTC2606)

Smallest Pin-Compatible Single DACs:

LTC2606: 16 Bits

LTC2616: 14 Bits

LTC2626: 12 Bits

Guaranteed 16-Bit Monotonic Over Temperature

27 Selectable Addresses

400kHz I

C Interface

Wide 2.7V to 5.5V Supply Range

Low Power Operation: 270μA at 3V

Power Down to 1μA, Max

High Rail-to-Rail Output Drive (±15mA, Min)

Double-Buffered Data Latches

Asynchronous DAC Update Pin

LTC2606/LTC2616/LTC2626: Power-On Reset to

Zero Scale

LTC2606-1/LTC2616-1/LTC2626-1: Power-On

Reset to Mid-Scale

Tiny (3mm × 3mm) 10-Lead DFN Package

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

DAC

INPUT

INTERFACE

16-BIT DAC

OUT

CONTROL

LOGIC

ADDRESS

DECODE

LDAC

SCL

SDA

CA0

CA1

CA2

2606 BD

GND

9 6

REF

CODE

0 16384 32768 49152 65535

DNL (LSB)

2606 G02

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Summary of content (20 pages)

PAGE 1
LTC2606/LTC2616/LTC2626 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface FEATURES DESCRIPTION n The LTC®2606/LTC2616/LTC2626 are single 16-, 14- and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic.
PAGE 2
LTC2606/LTC2616/LTC2626 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Any Pin to GND ............................................– 0.3V to 6V Any Pin to VCC ............................................ –6V to 0.3V Maximum Junction Temperature...........................125°C Storage Temperature Range...................–65°C to 125°C Lead Temperature (Soldering, 10 sec) ..................300°C Operating Temperature Range: LTC2606C/LTC2616C/LTC2626C LTC2606-1C/LTC2616-1C/LTC2626-1C ......
PAGE 3
LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted.
PAGE 4
LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. (Note 11) SYMBOL PARAMETER CONDITIONS MIN PSR Power Supply Rejection VCC = ±10% ROUT DC Output Impedance VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA VREF = VCC = 2.7V, Mid-Scale; –7.
PAGE 5
LTC2606/LTC2616/LTC2626 ELECTRICAL CHARACTERISTICS The ● denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 MIN MIN MIN TYP MAX TYP MAX TYP MAX UNITS AC Performance tS Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.
PAGE 6
LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 0.6 16 VCC = 5V VREF = 4.096V 24 16 0.4 0 –8 0.2 0 –0.2 0 –8 –0.4 –16 INL (POS) 8 INL (LSB) DNL (LSB) INL (LSB) 8 INL (NEG) –16 –0.6 –24 –32 –24 –0.8 16384 0 32768 CODE 49152 65535 –1.0 0 16384 32768 CODE 49152 2606 G01 1.5 VCC = 5.5V 24 0.6 90 VCC = 5.5V 1.
PAGE 7
LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2616 Integral Nonlinearity (INL) 8 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 6 0.6 0.4 2 DNL (LSB) INL (LSB) VCC = 5V VREF = 4.096V 0.8 4 0 –2 VOUT 100μV/DIV 0.2 0 9TH CLOCK OF 3RD DATA BYTE SCL 2V/DIV –0.2 –0.4 –4 –0.6 –6 –8 Settling to ±1LSB 4096 8192 CODE 12288 –1.0 16383 2606 G11 2μs/DIV –0.8 0 8.9μs 0 4096 8192 CODE 12288 2606 G09 VCC = 5V, VREF = 4.
PAGE 8
LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Zero-Scale Error vs Temperature Gain Error vs Temperature 3 3 0.3 2.0 1.5 1.0 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 2.5 ZERO-SCALE ERROR (mV) Offset Error vs VCC 0.4 0.1 0 –0.1 0 –1 –0.2 0.5 –2 –0.3 0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 2606 G20 0.4 –3 2.5 90 3.5 3 4 VCC (V) 4.5 5 2606 G21 Gain Error vs VCC 5.
PAGE 9
LTC2606/LTC2616/LTC2626 TYPICAL PERFORMANCE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Power-On Reset to Mid-Scale Supply Current vs Logic Voltage Supply Current vs Logic Voltage 650 VREF = VCC 1.2 VCC = 5V SWEEP LDAC 0V TO VCC 600 VCC = 5V SWEEP SCL AND SDA 0V TO VCC AND VCC TO 0V 1.1 1.0 550 0.9 1V/DIV ICC (μA) ICC (μA) 500 450 400 VCC 350 VOUT 300 HYSTERESIS 370mV 0.8 0.7 0.6 0.5 0.4 500μs/DIV 2606 G29 0.3 – 250 0 0.5 1 4 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4.5 0.2 5 0 0.
PAGE 10
LTC2606/LTC2616/LTC2626 PIN FUNCTIONS CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND or leave it ﬂoating to select an I2C slave address for the part (Table 1). SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open-drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. SCL (Pin 3): Serial Clock Input Pin.
PAGE 11
LTC2606/LTC2616/LTC2626 BLOCK DIAGRAM 3 9 6 VCC REF SCL INPUT REGISTER DAC REGISTER VOUT 16-BIT DAC 7 I2C INTERFACE SDA 2 CONTROL LOGIC 4 5 1 CA0 I2C ADDRESS DECODE CA1 CA2 LDAC GND 10 8 2606 BD TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD RINH/RINL/RINF 100Ω CAn CAn VIH(CAn)/VIL(CAn) GND 2606 TC 26061626fb 11
PAGE 12
2 1 SCL 3 A4 4 A3 5 A2 SLAVE ADDRESS 6 A1 7 A0 8 tf tHD(STA) tr tHD(DAT) tHIGH tSU(DAT) tf tSU(STA) 9 ACK 1 C3 2 C2 3 C1 4 C0 5 X 1ST DATA BYTE LDAC SCL 6 X 7 X 1 2 Figure 2b t1 Figure 2a 9 ACK 9TH CLOCK OF 3RD DATA BYTE 8 X S Figure 1 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS S tLOW 3 2606 F02b 4 5 2ND DATA BYTE tHD(STA) 6 7 tSU(STO) tSP 8 tr 9 ACK P 1 tBUF S 2 3 2606 F01 4 5 3RD DATA BYTE 6 7 8 9 ACK t1
PAGE 13
LTC2606/LTC2616/LTC2626 OPERATION Power-On Reset The LTC2606/LTC2616/LTC2626 clear the outputs to zero-scale when power is ﬁrst applied, making system initialization consistent and repeatable. The LTC2606-1/ LTC2616-1/LTC2626-1 set the voltage outputs to mid-scale when power is ﬁrst applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time.
PAGE 14
LTC2606/LTC2616/LTC2626 OPERATION Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC, GND or ﬂoat. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 1. Table 1.
PAGE 15
LTC2606/LTC2616/LTC2626 OPERATION Write Word Protocol for LTC2606/LTC2616/LTC1626 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE C2 C1 C0 X X 3RD DATA BYTE A P INPUT WORD Input Word (LTC2606) C3 A X X 1ST DATA BYTE D15 D14 D13 D12 D11 D10 D9 2ND DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 D0 3RD DATA BYTE Input Word (LTC2616) C3 C2 C1 C0 X X X X 1ST DATA BYTE D13 D12 D11 D10 D9 D8 D7 2ND DATA BYTE D6 D5 D4 D3 D2 D1 D0 X X X X 3RD DATA BYTE Input Word (LTC2626) C3 C2
PAGE 16
LTC2606/LTC2616/LTC2626 OPERATION The DAC is powered up when LDAC is taken low, independent of any activity on the I2C bus. If LDAC is low at the falling edge of the 9th clock of the 3rd byte of data, it inhibits any software power-down command that was speciﬁed in the input word. Voltage Output The rail-to-rail ampliﬁer has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V).
PAGE 17
X = DON’T CARE 2 1 SCL VOUT A5 A6 SDA A5 0V OUTPUT VOLTAGE 4 NEGATIVE OFFSET 3 A3 A3 6 A1 A1 7 A0 A0 1 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 X X COMMAND 6 X X 7 X X 8 X X 9 ACK 1 D15 2 D14 3 D13 4 5 D11 MS DATA D12 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 (b) OUTPUT VOLTAGE 0 (a) 32, 768 INPUT CODE VREF = VCC 65, 535 3 D5 4 INPUT CODE (c) 5 D3 LS DATA D4 VREF = VCC Figure 4.
PAGE 18
LTC2606/LTC2616/LTC2626 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev B) 0.70 p0.05 3.55 p0.05 1.65 p0.05 2.15 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p0.10 (4 SIDES) R = 0.125 TYP 6 0.40 p 0.10 10 1.65 p 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN REV B 0309 5 0.200 REF 1 0.25 p 0.05 0.50 BSC 0.75 p0.05 0.00 – 0.05 2.38 p0.
PAGE 19
LTC2606/LTC2616/LTC2626 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 11/09 Insert Text in Serial Digital Interface Section 13 26061626fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 20
LTC2606/LTC2616/LTC2626 TYPICAL APPLICATION Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters 5V 5V VREF 1V TO 5V 0.1μF CA0 I 2C BUS CA1 CA2 10 4 2 3 5 1 9 6 LDAC VCC VREF CA0 SDA LTC2606 VOUT SCL CA1 GND CA2 8 0.1μF 2 FSSET 7 100Ω 7.