Datasheet

LTC2604/LTC2614/LTC2624
11
2604fd
OPERATION
C3
COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS)
C2
C1
C0
A3
A2
A1
A0
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0 X XXX
2604 TBL03
MSB
LSB
C3
COMMAND ADDRESS DATA (14 BITS + 2 DON’T-CARE BITS)
C2
C1
C0
A3
A2
A1
A0
D13
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0 X X
2604 TBL02
MSB
LSB
C3
COMMAND ADDRESS DATA (16 BITS)
C2
C1
C0
A3
A2
A1
A0
D13D14D15
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
2604 TBL01
MSB
LSB
INPUT WORD (LTC2604)
INPUT WORD (LTC2614)
INPUT WORD (LTC2624)
Power Supply Sequencing
The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REF x ≤ V
CC
+ 0.3V (see Abso-
lute Maximum Ratings). Particular care should be taken
to observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
CC
(Pin 16) is
in transition.
Transfer Function
The digital-to-analog transfer function is
V
OUT(IDEAL)
=
k
2
N






[REF x – REF LO]+REFLO
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF
A, REF B, REF C and REF D (Pins 3, 6, 12 and 15).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded fi rst; then the 4-bit
DAC address, A3-A0; and fi nally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2604, LTC2614 and LTC2624 respectively). Data can
only be transferred to the device when the CS/LD signal
is low. The rising edge of CS/LD ends the data transfer
and causes the device to carry out the action specifi ed in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
Table 1.
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register n
0 0 0 1 Update (Power Up) DAC Register n
0 0 1 0 Write to Input Register n, Update (Power Up) All n
0 0 1 1 Write to and Update (Power Up) n
0 1 0 0 Power Down n
1 1 1 1 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
1 1 1 1 All DACs
*Command and address codes not shown are reserved and should not
be used.