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LTC4267

4267fc

Power over Ethernet

IEEE 802.3af PD Interface with

Integrated Switching Regulator

The LTC

4267 combines an IEEE 802.3af compliant Pow-

ered Device (PD) interface with a current mode switching

regulator, providing a complete power solution for PD

applications. The LTC4267 integrates the 25kΩ signature

resistor, classiﬁ cation current source, thermal overload pro-

tection, signature disable and power good signal along with

an undervoltage lockout optimized for use with the IEEE-

required diode bridge. The precision dual level input current

limit allows the LTC4267 to charge large load capacitors

and interface with legacy PoE systems.

The current mode switching regulator is designed for

driving a 6V rated N-channel MOSFET and features pro-

grammable slope compensation, soft-start, and constant

frequency operation, minimizing noise even with light

loads. The LTC4267 includes an onboard error ampliﬁ er

and voltage reference allowing use in both isolated and

nonisolated conﬁ gurations.

The LTC4267 is available in space saving, low proﬁ le

16-pin SSOP or DFN packages.

■

IP Phone Power Management

■

Wireless Access Points

■

Security Cameras

■

Power over Ethernet

■

Complete Power Interface Port for IEEE 802

.3af

Powered Device (PD)

■

Onboard 100V, 400mA UVLO Switch

■

Precision Dual Level Inrush Current Limit

■

Integrated Current Mode Switching Regulator

■

Onboard 25kΩ Signature Resistor with Disable

■

Programmable Classiﬁ cation Current (Class 0-4)

■

Thermal Overload Protection

■

Power Good Signal

■

Integrated Error Ampliﬁ er and Voltage Reference

■

Low Proﬁ le 16-Pin SSOP and 3mm × 5mm DFN

Packages

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Class 2 PD with 3.3V Isolated Power Supply

VCC

PWRGD

NGATE

SENSE

/RUN

PGND

OUT

PORTP

CLASS

SIGDISA

PORTN

LTC4267

CLASS

68.1Ω

5µF

MIN

10k

470

100k

60.4k

VCC

4.7µF

320µF

MIN

22nF

•

PA1133

PS2911

BAS516

TLV431

SBM1040

SMAJ58A

3.3V

1.5A

CHASSIS

HD01

–

HD01

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

4267 TA01

Si3440

0.1Ω

6.8k

10k

0.1µF

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Summary of content (32 pages)

PAGE 1
LTC4267 Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete Power Interface Port for IEEE 802®.
PAGE 2
LTC4267 W W U W ABSOLUTE AXI U RATI GS (Note 1) VPORTN with Respect to VPORTP Voltage ... 0.3V to –100V POUT, SIGDISA, ⎯P⎯W⎯R⎯G⎯D Voltage..................... VPORTN + 100V to VPORTN –0.3V PVCC to PGND Voltage (Note 2) Low Impedance Source ........................... –0.3V to 8V Current Fed .......................................... 5mA into PVCC RCLASS Voltage .................VPORTN + 7V to VPORTN – 0.3V ⎯P⎯W⎯R⎯G⎯D Current .....................................................10mA RCLASS Current.....
PAGE 3
LTC4267 ELECTRICAL CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T = 25°C.
PAGE 4
LTC4267 ELECTRICAL CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
PAGE 5
LTC4267 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range 0.5 Input Current vs Input Voltage 50 TA = 25°C Input Current vs Input Voltage 12.0 TA = 25°C CLASS 4 11.5 0.3 0.2 INPUT CURRENT (mA) 40 INPUT CURRENT (mA) INPUT CURRENT (mA) 0.4 CLASS 3 30 CLASS 2 20 CLASS 1 0.1 CLASS 1 OPERATION 10 11.0 85°C 10.5 –40°C 10.0 9.
PAGE 6
LTC4267 U W TYPICAL PERFOR A CE CHARACTERISTICS Reference Voltage vs Temperature 240 801.0 PVCC = 8V TA = 25°C PVCC ≤ VCLAMP1mA 800.8 800.6 VFB VOLTAGE (mV) VFB VOLTAGE (mV) 808 OSCILLATOR FREQUENCY (kHz) 812 Oscillator Frequency vs Temperature Reference Voltage vs Supply Voltage 804 800 796 800.4 800.2 800.0 799.8 799.6 799.4 792 PVCC = 8V (WITH RESPECT TO PGND) 230 220 210 200 190 799.2 788 –50 –30 –10 10 30 50 70 90 6 TEMPERATURE (°C) 6.
PAGE 7
LTC4267 U W TYPICAL PERFOR A CE CHARACTERISTICS Start-Up IPVCC Supply Current vs Temperature ITH/RUN Start-Up Current Source vs Temperature 450 SHUTDOWN THRESHOLD (mV) 50 40 30 20 10 600 ITH/RUN PIN CURRENT SOURCE (nA) PVCC = VTURNON – 0.1V 400 350 300 250 200 150 0 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 100 –50 –30 –10 10 30 50 70 90 500 400 300 200 100 0 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 4267 G21 Soft-Start Time vs Temperature 4.0 PVCC = 8V 3.5 110 3.
PAGE 8
LTC4267 U U U PI FU CTIO S (GN/DHC) ITH/RUN (Pin 2/Pin 1): Current Threshold/Run Input. This pin performs two functions. It serves as the switching regulator error ampliﬁer compensation point as well as the run/shutdown control input. Nominal voltage range is 0.7V to 1.9V. Forcing the pin below 0.28V with respect to PGND causes the controller to shut down. ⎯ W ⎯ R ⎯ G ⎯ D ⎯ (Pin 11/Pin 11): Power Good Output, Open-Drain.
PAGE 9
LTC4267 BLOCK DIAGRAM VPORTP PVCC SIGDISA CLASSIFICATION CURRENT LOAD 1.237V + – RCLASS 0.3µA 0.28V 25k SIGNATURE RESISTOR EN 9k 800mV REFERENCE VCC SHUNT REGULATOR + SHUTDOWN COMPARATOR – 16k PWRGD CONTROL CIRCUITS + + EN SHUTDOWN SOFTSTART CLAMP POWER GOOD 375mA PVCC < VTURNON UNDERVOLTAGE LOCKOUT ERROR AMPLIFIER + VFB INPUT CURRENT LIMIT – CURRENT COMPARATOR R Q S – PVCC SWITCHING LOGIC AND BLANKING CIRCUIT NGATE GATE DRIVER ITH/RUN 140mA 20mV – 1.
PAGE 10
LTC4267 U W U U APPLICATIO S I FOR ATIO speciﬁed to avoid corrupting the 25kΩ signature resistor while also saving board space and cost. In addition, the inrush current limit requirement of the IEEE 802.3af standard can cause large transient power dissipation in the PD. The LTC4267 is designed to allow multiple turn-on sequences without overheating the miniature 16-lead package.
PAGE 11
LTC4267 U W U U APPLICATIO S I FOR ATIO Series Diodes The signature range extends below the IEEE range to accommodate the voltage drop of the two diodes. The IEEE speciﬁcation requires the PSE to use a ΔV/ΔI measurement technique to keep the DC offset of these diodes from affecting the signature resistance measurement. However, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the PD.
PAGE 12
LTC4267 U W U U APPLICATIO S I FOR ATIO CURRENT PATH LTC4267 TO PSE VPORTP 9k 25k SIGNATURE RESISTOR 16k PSE PROBING VOLTAGE SOURCE –15.5V TO –20.5V SIGNATURE DISABLE SIGDISA LTC4267 RCLASS VPORTP RCLASS VPORTN VPORTN 4267 F03 4267 F04 V CONSTANT LOAD CURRENT INTERNAL TO LTC4267 PSE CURRENT MONITOR Figure 3. 25k Signature Resistor with Disable Classiﬁcation PD Figure 4. IEEE 802.3af Classiﬁcation Probing Once the PSE has detected a PD, the PSE may optionally classify the PD.
PAGE 13
LTC4267 U W U U APPLICATIO S I FOR ATIO the classiﬁcation current is reenabled. C1 will discharge through the PD circuitry and the POUT pin will go to a high impedance state. LTC4267 TO PSE UNDERVOLTAGE LOCKOUT CIRCUIT VPORTN VPORTP C1 5µF MIN + PGND POUT INPUT LTC4267 VOLTAGE POWER MOSFET 0V TO UVLO* OFF >UVLO* ON *UVLO INCLUDES HYSTERESIS RISING INPUT THRESHOLD ≅ –36V FALLING INPUT THRESHOLD ≅ –30.5V 4267 F05 CURRENT-LIMITED TURN ON Figure 5.
PAGE 14
LTC4267 U W U U APPLICATIO S I FOR ATIO LTC4267 PWRGD R9 100k THERMAL SHUTDOWN UVLO – TO PSE + PGND + – C1 5µF MIN PWRGD LTC4267 + –48V C1 R18 5µF 10k 100V C15 0.047µF D6 MMBD4148 LTC3803 GND OPTIONAL AUXILIARY SWITCHING REGULATOR POUT PGND ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP 300k POUT ITH/RUN C17 + PGND VPORTN Q1 FMMT2222 R9 100k VPORTP 1.125V 300k VPORTN ITH/RUN TO PSE ITH/RUN PGND RSTART 4267 F06 Figure 6.
PAGE 15
LTC4267 U W U U APPLICATIO S I FOR ATIO temperature exceeds the overtemperature trip point, the current is reduced to zero and very little power is dissipated in the part until it cools below the overtemperature set point. Once the LTC4267 has charged up the load capacitor and the PD is powered and running, there will be minor residual heating due to the DC load current of the PD ﬂowing through the internal MOSFET.
PAGE 16
LTC4267 U W U U APPLICATIO S I FOR ATIO The undervoltage lockout mechanism on PVCC prevents the LTC4267 switching regulator from trying to drive the external N-Channel MOSFET with insufﬁcient gate-toLTC4267 PWM SHUTDOWN PVCC < VTURNOFF ALL VOLTAGES WITH RESPECT TO PGND VITH/RUN < VITHSHDN (NOMINALLY 0.28V) VITH/RUN > VITHSHDN AND PVCC > VTURNON (NOMINALLY 8.
PAGE 17
LTC4267 U W U U APPLICATIO S I FOR ATIO Diode Bridge IEEE 802.3af allows power wiring in either of two conﬁgurations: on the TX/RX wires or via the spare wire pairs in the RJ45 connector. The PD is required to accept power in either polarity on either the main or spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring conﬁgurations. Figure 9 demonstrates an implementation of these diode bridges. The IEEE 802.
PAGE 18
LTC4267 U W U U APPLICATIO S I FOR ATIO RJ45 1 TX+ 16 T1 1 TX– 2 RX+ 3 RX– 6 15 2 14 11 3 6 10 7 9 8 BR1 HD01 TO PHY PULSE H2019 SPARE+ 4 BR2 HD01 5 7 VPORTP C14 0.1µF 100V SPARE– 8 LTC4267 D3 SMAJ58A TVS VPORTN 4267 F09 Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor D11 B1100 D9 B1100 R2 75Ω C3 0.01µF 200V R1 75Ω C7 0.
PAGE 19
LTC4267 U W U U APPLICATIO S I FOR ATIO Signature Disable Interface To disable the 25kΩ signature resistor, connect SIGDISA pin to the VPORTP pin. Alternately, SIGDISA pin can be driven high with respect to VPORTN. An example of a signature disable interface is shown in Figure 16, option 2. Note that the SIGDISA input resistance is relatively large and the threshold voltage is fairly low.
PAGE 20
LTC4267 U W U U APPLICATIO S I FOR ATIO Choose resistance values for R1 and R2 to be as large as possible to minimize any efﬁciency loss due to the static current drawn from VOUT, but just small enough so that when VOUT is in regulation, the error caused by the nonzero input current from the output of the resistor divider to the error ampliﬁer pin is less than 1%.
PAGE 21
LTC4267 U W U U APPLICATIO S I FOR ATIO ISOLATED DESIGN EXAMPLE –48V FROM DATA PAIR + VOUT • C1 RSTART – D1 T1 VPORTP LPRI PGND PVCC COUT LSEC • CPVCC PVCC VPORTP 0.1µF 100V –48V FROM SPARE PAIR – NGATE Q1 RSL RCLASS RCLASS + PGND VPORTN RLIM SENSE LTC4267 SIGDISA VPORTN RSENSE PGND VPORTP VFB ITH/RUN POUT OPTOISOLATOR PGND PVCC PGND ERROR AMPLIFIER RC CC R2 R1 PGND CISO NONISOLATED DESIGN EXAMPLE T1 LBIAS D2 –48V FROM DATA PAIR • + R3 RSTART – 0.
PAGE 22
LTC4267 U W U U APPLICATIO S I FOR ATIO Programmable Slope Compensation The LTC4267 switching regulator injects a ramping current through its SENSE pin into an external slope compensation resistor (RSL in Figure 11). This current ramp starts at zero after the NGATE pin has been high for the LTC4267’s minimum duty cycle of 6%. The current rises linearly towards a peak of 5µA at the maximum duty cycle of 80%, shutting off once the NGATE pin goes low.
PAGE 23
LTC4267 U W U U APPLICATIO S I FOR ATIO The shunt regulator can sink up to 5mA through the PVCC pin to PGND. The values of RSTART and CPVCC must be selected for the application to withstand the worst-case load conditions and drop on PVCC, ensuring that the PVCC turn-off threshold is not reached. CPVCC should be sized sufﬁciently to handle the switching current needed to drive NGATE while maintaining minimum switching voltage.
PAGE 24
LTC4267 U W U U APPLICATIO S I FOR ATIO of the LTC4267. In this case, it is necessary to ensure the user cannot access the terminals of the wall transformer jack on the PD since this would compromise the 802.3af isolation safety requirements. LTC4267 ITH/RUN CC PGND RZ 4267 F15 Figure 15.
PAGE 25
LTC4267 U W U U APPLICATIO S I FOR ATIO OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267 PD RJ45 1 2 3 6 TX+ T1 ~ TX– RX+ BR1 HD01 TO PHY ~ RX– D3 SMAJ58A TVS + C14 0.1µF 100V RSTART – C1 VPORTP SPARE+ 4 ~ 5 PVCC + LTC4267 BR2 HD01 7 SPARE– 8 ~ CPVCC PGND – VPORTN POUT PGND + D8 S1B ISOLATED WALL 38V TO 57V TRANSFORMER – OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267 PD WITH SIGNATURE DISABLED RJ45 1 2 3 6 TX+ TX T1 ~ – RX+ + ~ 100k C14 0.
PAGE 26
LTC4267 U W U U APPLICATIO S I FOR ATIO transformer voltage is higher than the PSE voltage, the LTC4267 switching regulator will draw power from the transformer. In this situation, it is necessary to address the issue of power cycling that may occur if a PSE is present. The PSE will detect the PD and apply power. If the switcher is being powered by the wall transformer, then the PD will not meet the minimum load requirement and the PSE will subsequently remove power.
PAGE 27
LTC4267 U W U U APPLICATIO S I FOR ATIO with minimum trace lengths and minimum capacitance. In a nonisolated application, R1, and R2 should be placed as close as possible to the VFB pin of the LTC4267 and CC should be placed close to the ITH/RUN pin of the LTC4267. or capacitive may inadvertently disable the signature resistance. To ensure consistent behavior, the SIGDISA pin should be electrically connected and not left ﬂoating.
PAGE 28
LTC4267 U TYPICAL APPLICATIO S Class 3 PD with 5V Nonisolated Power Supply COILTRONICS CTX-02-15242 5µF* MIN –48V FROM DATA PAIR BAS516 VPORTP – FDC2512 RCLASS + HD01 – 150pF 200V PWRGD 10k –48V FROM SPARE PAIR • 1µF NGATE 0.1µF 9.1V PVCC LTC4267 SMAJ58A 300µF** • MMBTA42 + HD01 UPS840 220k 100k 5V 1.8A 45.3Ω 1% ITH/RUN 22nF VPORTN *1µF CERAMIC + 4.7µF TANTALUM ** THREE 100µF CERAMICS 0.04Ω 1% 42.2k 1% VFB SIGDISA POUT 220Ω SENSE PGND 27k 4267 TA03 8.
PAGE 29
1 2 3 4 5 6 7 8 TO PHY TO PHY 0.1µF 45.3Ω SMAJ58A J1 HALO HFJ11 RP28E-L12 INTEGRATED JACK T1 COILCRAFT D1766-AL T2 PULSE PA0184 * TWO 100µF CAPACITORS IN PARALLEL ** 47µF AND 220µF IN PARALLEL *** 1µF CERAMIC + 4.7µF TANTALUM J1 9 10 11 12 13 14 PGND VFB VPORTN POUT ITH/RUN SENSE PWRGD SIGDISA RCLASS PVCC 220k NGATE LTC4267 VPORTP 5µF*** MIN 4.7µF PVCC BCX5616 8.2k 10p 51Ω BAS516 6.8k PVCC 10Ω BAS516 8.2V 220k 0.1µF 2.2k 0.
PAGE 30
LTC4267 U PACKAGE DESCRIPTIO DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 16 8 1 (DHC16) DFN 1103 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5.
PAGE 31
LTC4267 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.
PAGE 32
LTC4267 TYPICAL APPLICATION High-Efﬁciency Class 3 PD with 3.3V Isolated Power Supply 10Ω PULSE PA1136 470pF SBM1040 3.3V 2.6A • 5µF* MIN 220k 330Ω 220k 510Ω 570µF** • CHASSIS MMTBA42 MMSD4148 –48V FROM DATA PAIR BAS516 150pF 9.1V VPORTP BAS516 PVCC PVCC • 4.7µF LTC4267 SMAJ58A B1100 (8 PLACES) Si3440 NGATE 10k 0.1µF SENSE RCLASS –48V FROM SPARE PAIR ITH/RUN 45.3Ω 1% 0.068Ω 1% PVCC 100k SIGDISA PWRGD 10k VPORTN POUT *1µF CERAMIC + 4.