Datasheet

LTC2480
25
2480fd
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the first and 24th rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not finished loading the last input
bit SPD of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration
is still kept. This is useful for systems not requiring all 24
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2480’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2480’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
EOCtest
), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
applicaTions inForMaTion
EN GS2 GS1 GS0 IM FA FB SPD
SDI*
DON’T CARE DON’T CARE
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBSIG
BIT 8
TEST EOC
(OPTIONAL)
TEST EOC
BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEPSLEEP
DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA
OUTPUT
CONVERSIONCONVERSIONSLEEP
2480 F09
<t
EOCtest
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
–
SCK
SDI
SDO
CS
GND
2 10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1µF
2.7V TO 5.5V
LTC2480
4-WIRE
SPI INTERFACE
Figure 9. Internal Serial Clock, Reduce Data Output Length