Datasheet

LTC2480
24
2480fd
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC
= 0), the device will exit the low power mode during the
EOC test. In order to allow the device to return to the low
power sleep state, CS must be pulled HIGH before the first
rising edge of SCK. In the internal SCK timing mode, SCK
goes HIGH and the device begins outputting data at time
t
EOCtest
after the falling edge of CS (if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW during the falling edge
of EOC). The value of t
EOCtest
is 12µs if the device is using
its internal oscillator. If f
O
is driven by an external oscillator
of frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
in seconds. If
CS is pulled HIGH before time t
EOCtest
, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. After the 24th rising edge, SDO goes HIGH (EOC
=
1),
SCK stays HIGH and a new conversion starts.
applicaTions inForMaTion
EN GS2 GS1 GS0 IM FA FB SPD
SDI*
DON’T CARE DON’T CARE
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB IM
BIT 4
TEST EOC
BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22
EOC
BIT 23
SLEEP
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2480 F08
<t
EOCtest
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
–
SCK
SDI
SDO
CS
GND
2 10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1µF
2.7V TO 5.5V
LTC2480
4-WIRE
SPI INTERFACE
Figure 8. Internal Serial Clock, Single Cycle Operation