LTC2480 16-Bit ∆Σ ADC with Easy Drive Input Current Cancellation Features n n n n n n n n n n n n n Description Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy Programmable Gain from 1 to 256 Integrated Temperature Sensor GND to VCC Input/Reference Common Mode Range Programmable 50Hz, 60Hz or Simultaneous 50Hz/60Hz Rejection Mode 2ppm (0.
LTC2480 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VCC) to GND....................... –0.3V to 6V Analog Input Voltage to GND........ –0.3V to (VCC + 0.3V) Reference Input Voltage to GND... –0.3V to (VCC + 0.3V) Digital Input Voltage to GND......... –0.3V to (VCC + 0.3V) Digital Output Voltage to GND....... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2480C................................................ 0°C to 70°C LTC2480I ............................................
LTC2480 Electrical Characteristics (Normal speed) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX Resolution (No Missing Codes) 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) l Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) l 2 1 10 Offset Error 2.
LTC2480 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) MIN , GND ≤ IN– = IN+ ≤ V TYP MAX UNITS l 140 dB Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC CC (Note 5) l 140 dB Input Common Mode Rejection 60Hz ±2% 2.
LTC2480 ANALOG INPUTs AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS 0V ≤ VIN ≤ VCC (Note 10) IIN Digital Input Current SCK CIN Digital Input Capacitance CS, fO, SDI MIN CIN Digital Input Capacitance SCK VOH High Level Output Voltage SDO IO = –800µA l VOL Low Level Output Voltage SDO IO = 1.
LTC2480 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS tLESCK External SCK Low Period (Note 10) l MIN tHESCK External SCK High Period (Note 10) l 125 tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) l l 0.61 (Note 10) l TYP MAX 125 UNITS ns ns 0.625 0.
LTC2480 Typical Performance Characteristics Integral Nonlinearity (VCC = 5V, VREF = 5V) 2 25°C 0 85°C –1 –2 1 –45°C, 25°C, 90°C 0 –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 –0.75 4 0 12 25°C VCC = 5V VREF = 5V VIN(CM) = 1.25V fO = GND 8 85°C –45°C –4 –8 2 12 85°C –4 12 12 NUMBER OF READINGS (%) 2 –0.75 1.8 2480 G07 85°C –45°C –4 –12 –1.25 1.25 –0.25 0.25 0.75 INPUT VOLTAGE (V) –0.75 –0.25 0.25 0.
LTC2480 Typical Performance Characteristics RMS Noise vs Input Differential Voltage 0.8 VCC = 5V VREF = 5V GAIN = 256 VIN(CM) = 2.5V TA = 25°C VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 0.9 0.7 0.6 0.5 1.0 0.8 0.7 0.6 0.4 2.5 –1 0 2 1 3 5 4 0.8 OFFSET ERROR (ppm OF VREF) 0.6 0.7 0.6 0.5 0.5 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 0.4 5.5 0 1 2 3 VREF (V) 0 –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2480 G16 0.2 0.1 0 –0.1 –0.2 –0.
LTC2480 Typical Performance Characteristics Temperature Sensor vs Temperature 5 VPTAT/VREF (V) 0.30 0.25 310 VCC = 5V fO = GND 4 0.35 On-Chip Oscillator Frequency vs Temperature 308 3 2 FREQUENCY (kHz) VCC = 5V VREF = 1.4V fO = GND TEMPERATURE ERROR (°C) 0.40 Temperature Sensor Error vs Temperature VREF = 1.4V 1 0 –1 –2 306 304 302 –3 –4 –30 0 30 60 TEMPERATURE (°C) 90 –5 –60 120 –30 30 60 0 TEMPERATURE (°C) On-Chip Oscillator Frequency vs VCC 304 302 2.5 3.0 3.5 4.
LTC2480 Typical Performance Characteristics Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) Conversion Current vs Output Data Rate 350 300 2 VCC = 5V VCC = 3V 250 1 25°C, 90°C 0 –1 200 100 –45°C –2 150 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 0 2480 G33 1 90°C 0 –1 –45°C, 25°C –2 –3 –1.25 –45°C, 25°C –1 –2 2 –3 –1.25 2.5 RMS = 0.86µV 10,000 CONSECUTIVE AVERAGE = 0.
LTC2480 Typical Performance Characteristics Offset Error vs VREF (2x Speed Mode) 250 150 100 0 VCC = 5V VIN = 0V VIN(CM) = GND fO = GND TA = 25°C 230 OFFSET ERROR (µV) 200 OFFSET ERROR (µV) 240 VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND TA = 25°C PSRR vs Frequency at VCC (2x Speed Mode) 220 –40 210 200 190 2 2.5 3 4 3.5 VCC (V) 4.5 5.5 5 160 1 0 2 4 3 VREF (V) –60 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2480 G43 0 VCC = 4.1V DC ±1.4V REF+ = 2.
LTC2480 Pin Functions long as CS is HIGH. A LOW-to-HIGH transition on CS during the data output transfer aborts the data transfer and starts a new conversion. SDO (Pin 7): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.
LTC2480 Timing Diagrams Timing Diagram Using Internal SCK CS t1 t2 SDO tKQMIN t3 tKQMAX SCK t7 t8 SDI 2480 TD1 SLEEP DATA IN/OUT CONVERSION Timing Diagram Using External SCK CS t1 t2 SDO t5 SCK tKQMIN t6 t4 t7 tKQMAX t8 SDI 2480 TD2 SLEEP DATA IN/OUT CONVERSION Applications Information Converter Operation CONVERT Converter Operation Cycle The LTC2480 is a low power, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface and automatic differential input
LTC2480 Applications Information While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device exits the low power mode and enters the data output state.
LTC2480 Applications Information CS SDO Hi-Z BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 EOC DMY SIG MSB B16 BIT 18 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB GS2 GS1 GS0 IM CONVERSION RESULT PREVIOUS CONFIGURATION BITS SCK SDI EN GS2 GS1 GS0 IM FA SLEEP FB SPD DON’T CARE DATA INPUT/OUTPUT CONVERSION 2480 F02 Figure 2. Input/Output Data Timing Table 1.
LTC2480 Applications Information Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V) GAIN 1 4 8 16 32 64 128 256 Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV 65536 65536 65536 65536 65536 65536 32768 16384 Counts Noise Free Resolution* UNIT Gain Error 5 5 5 5 5 5 5 8 Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ppm of FS µV UNIT Table 2b.
LTC2480 Applications Information Output Data Format The LTC2480 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 17 bits are the conversion result, MSB first. The remaining 4 bits indicate the configuration state associated with the current conversion result.
LTC2480 Applications Information In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes in real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK.
LTC2480 Applications Information Table 5. LTC2480 State Duration STATE OPERATING MODE CONVERT Internal Oscillator External Oscillator DURATION 60Hz Rejection 133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode 67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode 50Hz Rejection 160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode 80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode 50Hz/60Hz Rejection 147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode 73.
LTC2480 Applications Information value with a temperature coefficient of 420/(27 + 273) = 1.40mV/°C (SLOPE), as shown in Figure 4. The internal PTAT signal is used in a single-ended mode referenced to device ground internally. The GAIN is automatically set to one (independent of the values of GS0, GS1, GS2) in order to preserve the PTAT property at the ADC output code and avoid an out of range error.
LTC2480 Applications Information Input signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN– pins without affecting the performance of the devices. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections.
LTC2480 Applications Information 2.7V TO 5.5V 1µF 2 VCC LTC2480 3 REFERENCE VOLTAGE 0.
LTC2480 Applications Information The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete.
LTC2480 Applications Information Internal Serial Clock, Single Cycle Operation rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 12µs if the device is using its internal oscillator. If fO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds.
LTC2480 Applications Information CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK (see Figure 9). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. If the device has not finished loading the last input bit SPD of SDI by the time CS is pulled HIGH, the SDI information is discarded and the previous configuration is still kept.
LTC2480 Applications Information Internal Serial Clock, 3-Wire I/O, Continuous Conversion period) then immediately begins outputting data. The data input/output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin.
LTC2480 Applications Information Digital Signal Levels The LTC2480’s digital interface is easy to use. Its digital inputs (SDI, fO, CS and SCK in External SCK mode of operation) accept standard CMOS logic levels and the internal hysteresis receivers can tolerate edge transition times as slow as 100µs. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter.
LTC2480 Applications Information Driving the Input and Reference period is 2.5/fEOSC and, for a settling error of less than 1ppm, τ ≤ 0.178/fEOSC. The input and reference pins of the LTC2480 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process.
LTC2480 Applications Information RSOURCE VINCM + 0.5VIN IN+ CEXT CPAR 20pF LTC2480 RSOURCE VINCM – 0.5VIN IN– CEXT CPAR 20pF 2480 F12 Figure 12. An RC Network at IN+ and IN– +FS ERROR (ppm) 80 VCC = 5V = 5V 60 VREF VIN+ = 3.75V – = 1.25V 40 VIN FO = GND 20 TA = 25°C CEXT = 0pF CEXT = 100pF 0 CEXT = 1nF, 0.1µF, 1µF –20 –40 –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2480 F13 Figure 13. +FS Error vs RSOURCE at IN+ or IN– –FS ERROR (ppm) 80 VCC = 5V = 5V 60 VREF VIN+ = 1.25V – 40 VIN = 3.
LTC2480 Applications Information voltage). Table 7 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages. Table 7. Suggested Input Configuration for LTC2480 BALANCED INPUT RESISTANCES UNBALANCED INPUT RESISTANCES Constant VIN(CM) – VREF(CM) CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance with Negligible Error CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance.
LTC2480 Applications Information 90 60 50 0 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF 40 30 20 –20 –30 –40 –50 VCC = 5V –60 VREF = 5V V + = 1.25V –70 VIN– = 3.75V IN –80 FO = GND TA = 25°C –90 10 0 10 0 –10 10 0 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF –10 –FS ERROR (ppm) 70 +FS ERROR (ppm) 10 VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C 80 1k 100 RSOURCE (Ω) 10k 100k 1k 100 RSOURCE (Ω) 10k 2480 F16 2480 F15 Figure 15.
LTC2480 Applications Information Output Data Rate internal oscillator and 50Hz mode, the extra gain error is 0.061ppm. If an external clock is used, the corresponding extra gain error is 0.24 • 10–6 • fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%.
LTC2480 Applications Information quency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2480’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins.
LTC2480 Applications Information The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2480 input bandwidth. When the internal oscillator is used with the notch set at 60Hz, the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the fO pin, the 3dB input bandwidth is 11.
LTC2480 Applications Information If the fO pin is driven by an external oscillator of frequency fEOSC, Figure 29 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 29 plot accuracy begins to decrease, but at the same time the LTC2480 noise floor rises and the noise contribution of the driving amplifiers lose significance.
LTC2480 Applications Information fEOSC/20. The performance of the normal mode rejection is shown in Figures 30 and 31. the LTC2480 for the 50Hz rejection mode and 50Hz/60Hz rejection mode are shown in Figures 35 and 36. In 1x speed mode, the regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth.
LTC2480 Applications Information VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) –20 –40 –60 –80 –20 –40 –60 –80 –100 –100 –120 0 INPUT NORMAL REJECTION (dB) NORMAL MODE REJECTION (dB) 0 –120 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 0 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 2480 F39 2480 F38 Figure 39.
LTC2480 Applications Information rejection identical as that for the 1x speed mode. The averaging operation still keeps the output rate with the following algorithm: Result 1 = average (sample 0, sample 1) Result 2 = average (sample 1, sample 2) …… Result n = average (sample n – 1, sample n) The main advantage of the running average is that it achieves simultaneous 50Hz/60Hz rejection at twice the effective output rate, as shown in Figure 42.
LTC2480 Applications Information /*** read_LTC2480() ************************************************************ This is the function that actually does all the work of talking to the LTC2480. The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus. Data changes state on falling clock edges and is valid on rising edges, as determined by the setup_spi() line in the initialize() function. A good starting point when porting to other processors is to write your own spi_write function.
LTC2480 package Description DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) R = 0.125 TYP 6 0.40 p 0.10 10 0.70 p0.05 3.55 p0.05 1.65 p0.05 2.15 p0.05 (2 SIDES) 3.00 p0.10 (4 SIDES) PACKAGE OUTLINE 0.25 p 0.05 1.65 p 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.75 p0.05 0.200 REF 0.50 BSC 2.38 p0.05 (2 SIDES) 5 0.00 – 0.05 1 (DD) DFN REV C 0310 0.25 p 0.05 0.50 BSC 2.38 p0.
LTC2480 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 11/09 Revised Tables 3 and 4. 17 C 04/10 Added H-Grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed), Electrical Characteristics (2x Speed), Converter Characteristics, Power Requirements, and Timing Characteristics.
LTC2480 Typical Application 5V C8 1µF PIC16F73 C7 0.
