Datasheet

LTC2439-1
7
24391fa
Figure 1
UU
W
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
V
CC
CH0
CH1
•
•
•
CH15
COM
IN
+
IN
–
MUX
SDO
SCK
REF
+
REF
–
CS
SDI
F
O
(INT/EXT)
24391 F01
+
–
1.69k
SDO
241418 TC01
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
241418 TA03
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
CONVERTER OPERATION
Converter Operation Cycle
The LTC2439-1 is a multichannel, low power, delta-sigma
analog-to-digital converter with an easy-to-use 4-wire se-
rial interface (see Figure 1). Its operation is made up of three
states. The converter operating cycle begins with the con-
version, followed by the low power sleep state and ends with
the data input/output (see Figure 2). The 4-wire interface
consists of serial data input (SDI), serial data output (SDO),
serial clock (SCK) and chip select (CS).
Initially, the LTC2439-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in the sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
APPLICATIO S I FOR ATIO
WUUU
Figure 2. LTC2439-1 State Transition Diagram
CONVERT
POWER UP
IN
+
= CH0, IN
–
= CH1
SLEEP
DATA OUTPUT
ADDRESS INPUT
24391 F02
TRUE
FALSE
CS = LOW
AND
SCK