Datasheet

LTC2439-1
24
24391fa
IN
–
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 15k source resistance will create
a 0LSB typical and 1LSB maximum offset voltage.
Reference Current
In a similar fashion, the LTC2439-1 samples the differen-
tial reference pins REF
+
and REF
–
transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F
O
= LOW
(internal oscillator and 50Hz/60Hz notch), the typical
differential reference resistance is 1.4MΩ which will gen-
erate a gain error of approximately 1LSB full scale for each
40Ω of source resistance driving REF
+
or REF
–
. When F
O
is driven by an external oscillator with a frequency f
EOSC
(external conversion clock operation), the typical differen-
tial reference resistance is 0.20 • 10
12
/f
EOSC
Ω and each
ohm of source resistance driving REF
+
or REF
–
will result
in 1.54 • 10
–7
• f
EOSC
LSB gain error at full scale. The effect
of the source resistance on the two reference pins is
additive with respect to this gain error. The typical +FS and
–FS errors for various combinations of source resistance
seen by the REF
+
and REF
–
pins and external capacitance
C
REF
connected to these pins are shown in Figures 19, 20,
21 and 22.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
O
= LOW (internal oscillator and 50Hz/60Hz notch),
every 1000Ω of source resistance driving REF
+
or REF
–
translates into about 1LSB additional INL error. When F
O
is driven by an external oscillator with a frequency f
EOSC
,
every 100Ω of source resistance driving REF
+
or REF
–
translates into about 5.5 • 10
–7
• f
EOSC
LSB additional INL
error. Figure 23 shows the typical INL error due to the
source resistance driving the REF
+
or REF
–
pins when
large C
REF
values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
+FS ERROR (LSB)
24361 F19
0
–3
–2
–1
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 5V
IN
–
= 2.5V
F
O
= GND
T
A
= 25°C
C
REF
= 0.01µF
C
REF
= 0.001µF
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
–FS ERROR (LSB)
2412 F19
3
0
1
2
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= GND
IN
–
= 2.5V
F
O
= GND
T
A
= 25°C
C
REF
= 0.01µF
C
REF
= 0.001µF
C
REF
= 100pF
C
REF
= 0pF
Figure 19. +FS Error vs R
SOURCE
at REF
+
or REF
–
(Small C
IN
)
Figure 20. –FS Error vs R
SOURCE
at REF
+
or REF
–
(Small C
IN
)
APPLICATIO S I FOR ATIO
WUUU