Datasheet

LTC2439-1
17
24391fa
APPLICATIO S I FOR ATIO
WUUU
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the conversion is complete.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
EOCtest
after the falling edge of CS (if EOC = 0) or t
EOCtest
after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
EOCtest
is 23µs if the device is using its internal
oscillator (F
O
= logic LOW or HIGH). If F
O
is driven by an
external oscillator of frequency f
EOSC
, then t
EOCtest
is
3.6/f
EOSC
. If CS is pulled HIGH before time t
EOCtest
, the
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 19th rising edge. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 19th rising edge of
SCK. After the 19th rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Figure 9. Internal Serial Clock, Single Cycle Operation
(1) (0) EN SGL A2 A1 A0
ODD/
SIGN
SDI
DON’T CARE DON’T CARE
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB
BIT 6
TEST EOC
BIT 14 BIT 13 BIT 12 BIT 11BIT 15BIT 16BIT 17
EOC
BIT 18
SLEEP
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
24391 F08
<t
EOCtest
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
1µF
2.7V TO 5.5V
LTC2439-1
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
V
CC
10k
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
“O”