Datasheet

LTC2439-1
16
24391fa
Figure 7. External Serial Clock, Reduced Data Output Length
(1) (0) EN SGL A2 A1 A0
ODD/
SIGN
SDI
DON’T CARE DON’T CARE
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSIONSLEEP
SLEEP
SLEEP
TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
24391 F06
MSBSIG
BIT 4BIT 14 BIT 13 BIT 12 BIT 11 BIT 5BIT 15BIT 16BIT 17
EOC
BIT 18BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
1µF
2.7V TO 5.5V
LTC2439-1
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
TEST EOC
(OPTIONAL)
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
“O”
APPLICATIO S I FOR ATIO
WUUU
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 19th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Figure 8. External Serial Clock, CS = 0 Operation
(1) (0) EN SGL A2 A1 A0
ODD/
SIGN
SDI
DON’T CARE DON’T CARE
EOC
BIT 18
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB
BIT 6BIT 14 BIT 13 BIT 12 BIT 11BIT 15BIT 16BIT 17
DATA OUTPUT CONVERSION
24391 F07
CONVERSION
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
1µF
2.7V TO 5.5V
LTC2439-1
3-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
“O”