Datasheet

LTC2412
25
2412f
APPLICATIO S I FOR ATIO
WUU
U
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C
IN
values, the settling on IN
+
and IN
–
occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN
+
or IN.
When F
O
= HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 2.16MΩ which will
generate a gain error of approximately 0.23ppm at full-
scale for each ohm of source resistance driving IN
+
or IN.
When F
O
is driven by an external oscillator with a fre-
quency f
EOSC
(external conversion clock operation), the
typical differential input resistance is 0.28 • 10
12
/f
EOSC
Ω
and each ohm of source resistance driving IN
+
or IN
–
will
result in 1.78 • 10
–6
• f
EOSC
ppm gain error at full-scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN
+
and IN
–
for large values of C
IN
are shown
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
–
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
–
pins. When F
O
= LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F
O
= HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a differ-
ential mode input signal of 0.23ppm. When F
O
is driven by
an external oscillator with a frequency f
EOSC
, every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10
–6
• f
EOSC
ppm. Figure 17 shows the
typical offset error due to input common mode voltage for
Figure 15. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 16. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
+FS ERROR (ppm OF V
REF
)
2412 F15
300
240
180
120
60
0
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 3.75V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
–FS ERROR (ppm OF V
REF
)
2412 F16
0
–60
–120
–180
–240
–300
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 1.25V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF