Datasheet

LTC4257-1
16
42571fb
APPLICATIO S I FOR ATIO
WUUU
that the transformer maintain the voltage between 38V and
57V to keep the LTC4257-1 in its normal operating range.
The third option has the advantage of automatically dis-
abling the 25k signature when the external voltage ex-
ceeds the PSE voltage.
Classification Resistor Selection (R
CLASS
)
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from R
CLASS
to
V
IN
(Figure 4) sets the value of the load current. The
designer should determine which power category the PD
falls into and then select the appropriate value of R
CLASS
from Table 2. If a unique load current is required, the value
of R
CLASS
can be calculated as:
R
CLASS
= 1.237V/(I
DESIRED
– I
IN_CLASS
)
where I
IN_CLASS
is the LTC4257-1 IC supply current
during classification and is given in the electrical speci-
fications. The R
CLASS
resistor must be 1% or better to
avoid degrading the overall accuracy of the classification
circuit. Resistor power dissipation will be 50mW maxi-
Figure 10. Power Good Interface Examples
mum and is transient so heating is typically not a con-
cern. In order to maintain loop stability, the layout should
minimize capacitance at the R
CLASS
node. The classifica-
tion circuit can be disabled by floating the R
CLASS
pin. The
R
CLASS
pin should not be shorted to V
IN
as this would
force the LTC4257-1 classification circuit to attempt to
source very large currents. In this case, the LTC4257-1
will quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
GND
C1
5µF
100V
V
IN
8
4
–48V
V
OUT
5
*C15 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
LTC4257-1
PD
LOAD
SHDN
PWRGD
6
D6
5.1V
MMBZ5231B
C15*
0.047µF
10V
R9
100k
R9
100k
R18
10k
R18
10k
+
GND
C1
5µF
100V
Q1
FMMT2222
D6
MMBD4148
V
IN
8
4
–48V
V
OUT
5
LTC4257-1
42571 F10
PD
LOAD
RUN
C17*
PWRGD
6
INTERNAL
PULLUP
+
ACTIVE-LOW ENABLE, 5.1V SWING
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
TO
PSE
TO
PSE
C15*
0.047µF
10V
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION