Datasheet
LTC2430/LTC2431
25
24301f
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN
+
and
IN
–
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2430 or LTC2431 samples the
differential reference pins REF
+
and REF
–
transfering small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01µF)
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sam-
pling charge and the external source resistance will see a
quasi constant reference differential impedance. When
F
O
= LOW (internal oscillator and 60Hz notch), the typical
differential reference resistance is 15.6MΩ which will
generate a gain error of approximately 0.032ppm for each
ohm of source resistance driving REF
+
or REF
–
. When F
O
= HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 18.7MΩ which will
generate a gain error of approximately 0.027ppm for each
ohm of source resistance driving REF
+
or REF
–
. When F
O
is driven by an external oscillator with a frequency f
EOSC
(external conversion clock operation), the typical differ-
ential reference resistance is 2.4 • 10
12
/f
EOSC
Ω and each
ohm of source resistance drving REF
+
or REF
–
will result
in 0.206 • 10
–6
• f
EOSC
ppm gain error. The effect of the
source resistance on the two reference pins is additive
with respect to this gain error. The typical FS errors for
various combinations of source resistance seen by the
REF
+
and REF
–
pins and external capacitance C
REF
con-
nected to these pins are shown in Figures 17 and 18.
Typical –FS errors are similar to +FS errors with opposite
polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF
+
or REF
–
translates
APPLICATIO S I FOR ATIO
WUUU
Figure 17b. –FS Error vs R
SOURCE
at REF
+
or REF
–
(Small C
IN
)
Figure 17a. +FS Error vs R
SOURCE
at REF
+
or REF
–
(Small C
IN
)
R
SOURCE
(Ω)
1
–50
+FS ERROR (ppm)
–40
–30
–20
–10
0
10
10 100 1k 10k
2431 F17a
100k
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
REF
=
0.01µF
C
REF
=
0pF
C
REF
=
0.001µF
C
REF
=
100pF
R
SOURCE
(Ω)
1
–10
–FS ERROR (ppm)
0
10
20
30
40
50
10 100 1k 10k
2431 F17b
100k
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
REF
=
0.01µF
C
REF
=
0pF
C
REF
=
0.001µF
C
REF
=
100pF