Datasheet

LTC2430/LTC2431
24
24301f
The typical +FS and –FS errors as a function of the sum of
the source resistance seen by IN
+
and IN
–
for large values
of C
IN
are shown in Figure 15.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
–
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
–
pins. When F
O
= LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.023ppm. When F
O
= HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.019ppm. When F
O
is
driven by an external oscillator with a frequency f
EOSC
,
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.15 • 10
–6
• f
EOSC
ppm. Figure 16
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN
+
and IN
–
pins when large C
IN
values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
APPLICATIO S I FOR ATIO
WUUU
Figure 15a. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 15b. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
R
SOURCE
(Ω)
0
+FS ERROR (ppm)
10
15
800
2431 F15a
5
0
200
400
500
1000
20
600
100
300
900
700
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
R
SOURCE
(Ω)
0
–FS ERROR (ppm)
–10
–5
800
2431 F15b
–15
–20
200
400
500
1000
0
600
100
300
900
700
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
Figure 16. Offset Error vs Common Mode Voltage
(V
INCM
= V
IN
+ = V
IN
–) and Input Source Resistance Imbalance
(∆R
IN
= R
SOURCEIN
+
– R
SOURCEIN
–
) for Large C
IN
Values (C
IN
≥ 1µF)
V
INCM
(V)
0
OFFSET ERROR (ppm)
0
20
4
–20
–40
1
2
2.5
5
40
A
B
C
D
E
F
G
3
0.5
1.5
4.5
3.5
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= V
IN
–
= V
INCM
F
O
= GND
R
SOURCEIN
–
= 500Ω
C
IN
= 10µF
T
A
= 25°C
2431 F16
A: ∆R
IN
= +1k
B: ∆R
IN
= +500Ω
C: ∆R
IN
= +200Ω
D: ∆R
IN
= 0Ω
E: ∆R
IN
= –200Ω
F: ∆R
IN
= –500Ω
G: ∆R
IN
= –1k