Datasheet
LTC2430/LTC2431
22
24301f
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the converter (LTC2430 or
LTC2431) are directly connected to a network of sampling
capacitors. Depending upon the relation between the dif-
ferential input voltage and the differential reference volt-
age, these capacitors are switching between these four
pins transfering small amounts of charge in the process.
A simplified equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
–
, REF
+
or REF
–
) can be
considered to form, together with R
SW
and C
EQ
(see
Figure␣ 11), a first order passive network with a time
constant τ = (R
S
+ R
SW
) • C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
O
= LOW or HIGH), the
LTC2430/LTC2431’s front-end switched-capacitor net-
work is clocked at 76800Hz corresponding to a 13µs
sampling period. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that τ ≤ 13µs/14 = 920ns. When an external oscillator
of frequency f
EOSC
is used, the sampling period is 2/f
EOSC
and, for a settling error of less than 1ppm, τ ≤ 0.14/f
EOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
–
pins as a result of the
APPLICATIO S I FOR ATIO
WUUU
Figure 11. LTC2430/LTC2431 Equivalent Analog Input Circuit
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
20k
C
EQ
6pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
2431 F11
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 76800Hz INTERNAL OSCILLATOR (F
O
= LOW OR HIGH)
f
SW
= 0.5 • f
EOSC
EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
20k
IIN
VV V
R
IIN
VV V
R
IREF
VV V
R
V
VR
I REF
VV V
R
V
VR
WHERE
AVG
IN INCM REFCM
EQ
AVG
IN INCM REFCM
EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
+
−
+
−
()
=
+−
•
()
=
−+ −
•
()
=
•− +
•
−
•
()
=
−• − +
•
+
•
05
05
15
05
15
05
2
2
.
.
.
.
.
.
::
.
.
./
V REF REF
V
REF REF
VININ
V
IN IN
R M INTERNAL OSCILLATOR Hz Notch F LOW
R M INTERNAL OSCILLATOR Hz Notch F HIGH
R f EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ O
EQ O
EQ EOSC
=−
=
+
=−
=
−
==
()
==
()
=•
()
+−
+−
+−
+−
2
2
43 2 60
52 0 50
666 10
12
Ω
Ω