Datasheet

LTC2430/LTC2431
13
24301f
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2430/LTC2431 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG MSB
V
IN
≥ 0.5 • V
REF
0011
0V ≤ V
IN
< 0.5 • V
REF
0010
–0.5 • V
REF
≤ V
IN
< 0V 0 0 0 1
V
IN
< –0.5 • V
REF
0000
Bits 20-0 are the 21-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 22) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater than
Table 2. LTC2430/LTC2431 Output Data Format
Differential Input Voltage Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 … Bit 0
V
IN
* EOC DMY SIG MSB LSB
V
IN
* ≥ 0.5 • V
REF
** 00110 0 0…0
0.5 • V
REF
** – 1LSB 00101 1 1…1
0.25 • V
REF
** 00101 0 0…0
0.25 • V
REF
** – 1LSB 00100 1 1…1
0 00100 0 0…0
–1LSB 0 0011 1 1…1
–0.25 • V
REF
** 00011 0 0…0
–0.25 • V
REF
** – 1LSB 00010 1 1…1
–0.5 • V
REF
** 00010 0 0…0
V
IN
* < –0.5 • V
REF
** 00001 1 1…1
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
Figure 3. Output Data Timing
MSBSIG“0”
1234524
BIT 0
LSB
BIT 19BIT 20BIT 21BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP
DATA OUTPUT CONVERSION
2431 F03
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