Datasheet

LTC2410
27
APPLICATIO S I FOR ATIO
WUU
U
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2410 samples the differential
reference pins REF
+
and REF
–
transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F
O
= LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3MΩ which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF
+
or REF
–
. When F
O
= HIGH (internal
oscillator and 50Hz notch), the typical differential refer-
ence resistance is 1.56MΩ which will generate a gain error
of approximately 0.32ppm for each ohm of source resis-
tance driving REF
+
or REF
–
. When F
O
is driven by an
external oscillator with a frequency f
EOSC
(external conver-
sion clock operation), the typical differential reference
resistance is 0.20 • 10
12
/f
EOSC
Ω and each ohm of source
resistance drving REF
+
or REF
–
will result in
2.47 • 10
–6
• f
EOSC
ppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
Figure 19. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 20. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 21. Offset Error vs Common Mode Voltage
(V
INCM
= IN
+
= IN
–
) and Input Source Resistance Imbalance
(∆R
IN
= R
SOURCEIN
+ – R
SOURCEIN
–) for Large C
IN
Values (C
IN
≥ 1µF)
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
+FS ERROR (ppm OF V
REF
)
2410 F19
300
240
180
120
60
0
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 3.75V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
–FS ERROR (ppm OF V
REF
)
2410 F20
0
–60
–120
–180
–240
–300
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 1.25V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
INCM
(V)
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OFFSET ERROR (ppm OF V
REF
)
2410 F21
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
F
O
= GND
T
A
= 25°C
R
SOURCEIN
– = 500Ω
C
IN
= 10µF
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= IN
–
= V
INCM
A: ∆R
IN
= +400Ω
B: ∆R
IN
= +200Ω
C: ∆R
IN
= +100Ω
D: ∆R
IN
= 0Ω
E: ∆R
IN
= –100Ω
F: ∆R
IN
= –200Ω
G: ∆R
IN
= –400Ω
A
B
C
D
E
F
G