Datasheet

LTC2410
14
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (F
O
)
The LTC2410 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejec-
tion, F
O
should be connected to GND while for 50Hz
rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
Table 2. LTC2410 Output Data Format
Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0
V
IN
* EOC DMY SIG MSB
V
IN
* ≥ 0.5 • V
REF
** 00110 0 0…0
0.5 • V
REF
** – 1LSB 00101 1 1…1
0.25 • V
REF
** 00101 0 0…0
0.25 • V
REF
** – 1LSB 00100 1 1…1
0 00100 0 0…0
–1LSB 0 0011 1 1…1
–0.25 • V
REF
** 00011 0 0…0
–0.25 • V
REF
** – 1LSB 00010 1 1…1
–0.5 • V
REF
** 00010 0 0…0
V
IN
* < –0.5 • V
REF
** 00001 1 1…1
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
Figure 3. Output Data Timing
APPLICATIO S I FOR ATIO
WUU
U
MSBSIG“0”
12345 262732
BIT 0BIT 27 BIT 5
LSB
24
BIT 28BIT 29BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2410 F03
Hi-Z